Patents by Inventor Masahisa Tamura

Masahisa Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200209719
    Abstract: An accessory configured to be detachably mountable to an image pickup apparatus including a first mount portion including first bayonet claw portions and first terminals, the accessory including a second mount portion including second bayonet claw portions configured to enable engagement with the first bayonet claw portions, and second terminals configured to enable contact with the first terminals, in which the second terminals are provided at positions that are different from positions of the second bayonet claw portions, and wherein half lines that extends from a central axis of the second mount portion and passes through second terminals that are used in communication between the image pickup apparatus and the accessory, all pass through a predetermined second bayonet claw portion.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Masahisa Tamura, Kunihiko Sasaki, Toshinori Yamazaki, Masayasu Shigematsu
  • Publication number: 20200201149
    Abstract: An accessory configured to be detachably mountable to an image pickup apparatus including a first mount portion including first bayonet claw portions, and first terminals, the accessory including a second mount portion including second bayonet claw portions configured to enable engagement with the first bayonet claw portions, and second terminals configured to enable contact with the first terminals, in which the second terminals are provided at positions that are different from positions of the second bayonet claw portions, and wherein, a half line that extends from a central axis of the second mount portion and passes through a second terminal that determines whether an optical apparatus is mounted on the image pickup apparatus or not, passes through a predetermined second bayonet claw portion.
    Type: Application
    Filed: March 5, 2020
    Publication date: June 25, 2020
    Inventors: Masahisa Tamura, Kunihiko Sasaki, Toshinori Yamazaki, Masayasu Shigematsu
  • Patent number: 10671579
    Abstract: An index generation request reception unit configured to receive an index generation request for stored data from one or more information processing apparatuses, and a determination unit configured to determine whether an index of data is generated or not in accordance with identification information attached to the index generation request are provided, so that writing of an object is efficiently processed.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: June 2, 2020
    Assignee: Fujitsu Limited
    Inventor: Masahisa Tamura
  • Publication number: 20200162744
    Abstract: An information processing system includes one or more processors configured to acquire a plurality of pieces of divided data generated by dividing the data, determine, in accordance with offset information, a first position of a first key point closest to a head position of each of the plurality of pieces of divided data, and a second position of a second key point closest to an end position of each of the plurality of pieces of divided data, generate first difference information indicating first data between the head position and the first position, and second difference information indicating second data between the end position and the second position, generate metadata to be used for decoding partial data, distribute the plurality of pieces of divided data to a plurality of nodes respectively together with the first difference information, the second difference information, and the metadata.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 21, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Iwata, Masahisa TAMURA
  • Patent number: 10627704
    Abstract: An accessory configured to be detachably mountable to an image pickup apparatus including a first mount portion including first bayonet claw portions and first terminals, the accessory including a second mount portion including second bayonet claw portions configured to enable engagement with the first bayonet claw portions, and second terminals configured to enable contact with the first terminals, in which the second terminals are provided at positions that are different from positions of the second bayonet claw portions, and wherein half lines that extends from a central axis of the second mount portion and passes through second terminals that are used in communication between the image pickup apparatus and the accessory, all pass through a predetermined second bayonet claw portion.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahisa Tamura, Kunihiko Sasaki, Toshinori Yamazaki, Masayasu Shigematsu
  • Patent number: 10620510
    Abstract: An accessory configured to be detachably mountable to an image pickup apparatus including a first mount portion including first bayonet claw portions, and first terminals, the accessory including a second mount portion including second bayonet claw portions configured to enable engagement with the first bayonet claw portions, and second terminals configured to enable contact with the first terminals, in which the second terminals are provided at positions that are different from positions of the second bayonet claw portions, and wherein, a half line that extends from a central axis of the second mount portion and passes through a second terminal that determines whether an optical apparatus is mounted on the image pickup apparatus or not, passes through a predetermined second bayonet claw portion.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 14, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahisa Tamura, Kunihiko Sasaki, Toshinori Yamazaki, Masayasu Shigematsu
  • Patent number: 10523219
    Abstract: The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 31, 2019
    Assignee: SONY CORPORATION
    Inventors: Masahisa Tamura, Shunsuke Sakazume, Takeshi Matsubara, Ken Yamamoto
  • Publication number: 20190305933
    Abstract: A blockchain method generates data on a new blockchain by linking a new block to data on a blockchain including a plurality of blocks linked together each being a set of data containing given information. The blockchain method may further includes: in generating a second block following a first block included in the data on the blockchain, identifying, among branch blocks approved prior to the generating of the second block, one or more blocks capable of being approved in parallel with the first block, and generating and registering, in a memory, the second block following the first block and the one or more blocks capable of being approved in parallel with the first block.
    Type: Application
    Filed: February 12, 2019
    Publication date: October 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Miyamae, Masahisa TAMURA
  • Patent number: 10419352
    Abstract: A non-transitory, computer-readable recording medium has stored therein a program for causing a computer to execute a process that includes: receiving packets captured from a network and allocating first groups in which the packets are classified in accordance with a first scheme to storage locations in a storage; allocating second groups in which the packets are classified in accordance with a second scheme to the storage locations in the storage; and selecting the second groups allocated to the storage as storage locations other than the storage locations to which the first groups to which the packets belong are allocated when the packets are classified in the second groups in accordance with the second scheme.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 17, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masahisa Tamura
  • Patent number: 10298478
    Abstract: An information processing system includes a plurality of information processing apparatuses connected to each other, and communication is performed between the plurality of information processing apparatuses. Each of the plurality of information processing apparatuses includes a processor.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 21, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masahisa Tamura
  • Publication number: 20190068205
    Abstract: The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area.
    Type: Application
    Filed: February 20, 2017
    Publication date: February 28, 2019
    Inventors: MASAHISA TAMURA, SHUNSUKE SAKAZUME, TAKESHI MATSUBARA, KEN YAMAMOTO
  • Publication number: 20180348473
    Abstract: An interchangeable lens assembly includes a plurality of lens-side claw portions configured to enable engagement with a plurality of camera-side claw portions, and a lock pin concave portion in which a lock pin is inserted. Furthermore, ?1 is an angle formed by a line passing through a fifth lens-side end and an optical axis, and a line passing through a center of a lock pin concave portion and the optical axis, and ?2 is an angle formed by a line passing through a fourth lens-side end and the optical axis, and a line that passes through the center of the lock pin concave portion and the optical axis. In the above, ?1 and ?2 satisfy a predetermined conditional expression.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 6, 2018
    Inventors: Kunihiko Sasaki, Toshinori Yamazaki, Masahisa Tamura, Masayasu Shigematsu
  • Publication number: 20180348611
    Abstract: An interchangeable lens assembly includes a plurality of lens-side claw portions and a lock pin concave portion. Furthermore, internal angles of a quadrangle formed by connecting a center of a first lens-side claw portion, a center of a second lens-side claw portion, a center of a third lens-side claw portion, and a center of the lock pin concave portion satisfies a predetermined condition.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 6, 2018
    Inventors: Toshinori Yamazaki, Kunihiko Sasaki, Masahisa Tamura, Masayasu Shigematsu
  • Publication number: 20180348610
    Abstract: An accessory configured to be detachably mountable to an image pickup apparatus including a first mount portion including first bayonet claw portions, and first terminals, the accessory including a second mount portion including second bayonet claw portions configured to enable engagement with the first bayonet claw portions, and second terminals configured to enable contact with the first terminals, in which the second terminals are provided at positions that are different from positions of the second bayonet claw portions, and wherein, a half line that extends from a central axis of the second mount portion and passes through a second terminal that determines whether an optical apparatus is mounted on the image pickup apparatus or not, passes through a predetermined second bayonet claw portion.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 6, 2018
    Inventors: Masahisa Tamura, Kunihiko Sasaki, Toshinori Yamazaki, Masayasu Shigematsu
  • Publication number: 20180348597
    Abstract: An accessory configured to be detachably mountable to an image pickup apparatus including a first mount portion including first bayonet claw portions and first terminals, the accessory including a second mount portion including second bayonet claw portions configured to enable engagement with the first bayonet claw portions, and second terminals configured to enable contact with the first terminals, in which the second terminals are provided at positions that are different from positions of the second bayonet claw portions, and wherein half lines that extends from a central axis of the second mount portion and passes through second terminals that are used in communication between the image pickup apparatus and the accessory, all pass through a predetermined second bayonet claw portion.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 6, 2018
    Inventors: Masahisa Tamura, Kunihiko Sasaki, Toshinori Yamazaki, Masayasu Shigematsu
  • Publication number: 20180181338
    Abstract: An information processing apparatus includes: a memory configured to store a storage controlling program; and a processor configured to execute a process based on the storage controlling program, wherein the process includes: storing, in the memory, address information regarding an address of a unit region for which duplicate deletion of data was performed in the past and data information regarding data in the unit region as past information; generating, using the address information, first data information of a first unit region in a state in which duplicate deletion of data has been performed currently; and specifying a data region to be a target of garbage collection based on the data information in the past information and the generated first data information.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Masahisa Tamura
  • Publication number: 20180077070
    Abstract: A non-transitory, computer-readable recording medium has stored therein a program for causing a computer to execute a process that includes: receiving packets captured from a network and allocating first groups in which the packets are classified in accordance with a first scheme to storage locations in a storage; allocating second groups in which the packets are classified in accordance with a second scheme to the storage locations in the storage; and selecting the second groups allocated to the storage as storage locations other than the storage locations to which the first groups to which the packets belong are allocated when the packets are classified in the second groups in accordance with the second scheme.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 15, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Masahisa TAMURA
  • Patent number: 9531383
    Abstract: A semiconductor device includes: a first signal generation section configured to generate an activation signal having a variable duty ratio; and a first processing section configured to perform intermittent operation, based on the activation signal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 27, 2016
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Masahisa Tamura
  • Patent number: 9430489
    Abstract: A computer includes a memory that stores a program and received data; and a processor that executes an operation by executing the program stored in the memory, the operation including storing the received data into a first database having a first data structure in which reading is performed in a random access manner and writing is performed in a sequential access manner, when the received data is received from a second apparatus is as same as data stored in a first apparatus which has a failure, and copying the received data stored in the first database to a second database having a second data structure in which reading is performed in a sequential access manner and writing is performed in a random access manner.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Ken Iizawa, Toshihiro Ozawa, Yasuo Noguchi, Kazuichi Oe, Munenori Maeda, Kazutaka Ogihara, Masahisa Tamura, Tatsuo Kumano, Jun Kato
  • Patent number: 9391622
    Abstract: An oscillator circuit includes: an arithmetic section configured to correct a first input code value and thereby generate a first code value that is within a first predetermined range, the arithmetic section being configured to correct a second input code value in correspondence with a correction amount of the first input code value and thereby generate a second code value, and the first predetermined range being narrower than a range of the first input code value; and an oscillation section configured to generate an oscillation signal having a frequency that varies at first sensitivity based on the first code value and varies at second sensitivity based on the second code value, the second sensitivity being higher than the first sensitivity.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 12, 2016
    Assignee: Sony Corporation
    Inventors: Masahisa Tamura, Hidenori Takeuchi