Patents by Inventor Masahito Kanamura
Masahito Kanamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9966445Abstract: A semiconductor device includes first, a second, and third semiconductor layers respectively made of a nitride semiconductor and stacked on a substrate, a drain electrode formed on the third semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode formed within an opening penetrating the third and second semiconductor layers and exposing the first semiconductor layer. The source electrode includes a first conductor layer in contact with the first semiconductor layer, and a second conductor layer stacked on the first conductor layer and in contact with the second semiconductor layer. A work function of a material forming the first conductor layer is smaller than that of a material forming the second conductor layer.Type: GrantFiled: August 29, 2016Date of Patent: May 8, 2018Assignee: FUJITSU LIMITEDInventor: Masahito Kanamura
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Patent number: 9608083Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.Type: GrantFiled: June 9, 2015Date of Patent: March 28, 2017Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
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Patent number: 9536967Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.Type: GrantFiled: December 16, 2014Date of Patent: January 3, 2017Assignee: Transphorm Inc.Inventors: Toshihide Kikkawa, Kenji Kiuchi, Tsutomu Hosoda, Masahito Kanamura, Akitoshi Mochizuki
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Publication number: 20160365419Abstract: A semiconductor device includes first, a second, and third semiconductor layers respectively made of a nitride semiconductor and stacked on a substrate, a drain electrode formed on the third semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode formed within an opening penetrating the third and second semiconductor layers and exposing the first semiconductor layer. The source electrode includes a first conductor layer in contact with the first semiconductor layer, and a second conductor layer stacked on the first conductor layer and in contact with the second semiconductor layer. A work function of a material forming the first conductor layer is smaller than that of a material forming the second conductor layer.Type: ApplicationFiled: August 29, 2016Publication date: December 15, 2016Applicant: FUJITSU LIMITEDInventor: Masahito KANAMURA
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Patent number: 9461135Abstract: A semiconductor device includes first, a second, and third semiconductor layers respectively made of a nitride semiconductor and stacked on a substrate, a drain electrode formed on the third semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode formed within an opening penetrating the third and second semiconductor layers and exposing the first semiconductor layer. The source electrode includes a first conductor layer in contact with the first semiconductor layer, and a second conductor layer stacked on the first conductor layer and in contact with the second semiconductor layer. A work function of a material forming the first conductor layer is smaller than that of a material forming the second conductor layer.Type: GrantFiled: November 24, 2014Date of Patent: October 4, 2016Assignee: FUJITSU LIMITEDInventor: Masahito Kanamura
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Publication number: 20160172455Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Inventors: Toshihide Kikkawa, Kenji Kiuchi, Tsutomu Hosoda, Masahito Kanamura, Akitoshi Mochizuki
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Patent number: 9349828Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; an insulating layer formed on the second semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; and a gate electrode formed on the insulating layer. The insulating layer is formed of a material including an oxide and is formed by laminating a first insulating layer and a second insulating layer in a positioning order of the first insulating layer followed by the second insulating layer from a side of the second semiconductor layer, and an amount of hydroxyl groups included in per unit volume of the first insulating layer is less than an amount of hydroxyl groups included in per unit volume of the second insulating layer.Type: GrantFiled: May 19, 2014Date of Patent: May 24, 2016Assignee: FUJITSU LIMITEDInventor: Masahito Kanamura
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Patent number: 9331190Abstract: An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.Type: GrantFiled: December 18, 2012Date of Patent: May 3, 2016Assignee: FUJITSU LIMITEDInventors: Masahito Kanamura, Toshihide Kikkawa
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Patent number: 9269782Abstract: A semiconductor device, comprising: a first semiconductor layer disposed on a substrate; a second semiconductor layer disposed on the first semiconductor layer; a lower insulating film disposed on the second semiconductor layer; a p-type electroconductive oxide film disposed on the lower insulating film; an upper insulating film disposed on the oxide film; and a gate electrode disposed on the upper insulating film, wherein the lower insulating film under the gate electrode has a depressed portion.Type: GrantFiled: September 7, 2012Date of Patent: February 23, 2016Assignee: FUJITSU LIMITEDInventors: Masahito Kanamura, Toyoo Miyajima, Toshihiro Ohki
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Publication number: 20150279956Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.Type: ApplicationFiled: June 9, 2015Publication date: October 1, 2015Applicant: FUJITSU LIMITEDInventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
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Publication number: 20150194514Abstract: On a surface of a compound semiconductor layer including inner wall surfaces of an electrode trench, an etching residue 12a and an altered substance 12b which are produced due to dry etching for forming the electrode trench are removed, and a compound semiconductor is terminated with fluorine. Gate metal is buried in the electrode trench via a gate insulating film, or the gate metal is directly buried in the electrode trench, whereby a gate electrode is formed.Type: ApplicationFiled: March 9, 2015Publication date: July 9, 2015Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Norikazu NAKAMURA, Toshihiro OHKI, Masahito KANAMURA
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Publication number: 20150162413Abstract: A semiconductor device includes first, a second, and third semiconductor layers respectively made of a nitride semiconductor and stacked on a substrate, a drain electrode formed on the third semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode formed within an opening penetrating the third and second semiconductor layers and exposing the first semiconductor layer. The source electrode includes a first conductor layer in contact with the first semiconductor layer, and a second conductor layer stacked on the first conductor layer and in contact with the second semiconductor layer. A work function of a material forming the first conductor layer is smaller than that of a material forming the second conductor layer.Type: ApplicationFiled: November 24, 2014Publication date: June 11, 2015Applicant: FUJITSU LIMITEDInventor: Masahito Kanamura
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Patent number: 8999772Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.Type: GrantFiled: October 23, 2014Date of Patent: April 7, 2015Assignee: Fujitsu LimitedInventors: Masahito Kanamura, Kozo Makiyama
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Publication number: 20150044825Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.Type: ApplicationFiled: October 23, 2014Publication date: February 12, 2015Inventors: Masahito Kanamura, Kozo Makiyama
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Patent number: 8941146Abstract: A compound semiconductor device includes an electron transit layer; an electron supply layer formed over the electron transit layer; a first recessed portion and a second recessed portion formed in the electron supply layer; a chemical compound semiconductor layer including impurities that buries the first recessed portion and the second recessed portion and covers over the electron supply layer; a source electrode formed over the chemical compound semiconductor layer which buries the first recessed portion; a drain electrode formed over the chemical compound semiconductor layer which buries the second recessed portion; and a gate electrode formed over the electron supply layer between the source electrode and the drain electrode, wherein, in the chemical compound semiconductor layer, a concentration of impurities included below the source electrode and the drain electrode is higher than a concentration of impurities included near the gate electrode.Type: GrantFiled: October 1, 2010Date of Patent: January 27, 2015Assignee: Fujitsu LimitedInventor: Masahito Kanamura
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Patent number: 8912571Abstract: A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film.Type: GrantFiled: November 11, 2011Date of Patent: December 16, 2014Assignee: Fujitsu LimitedInventors: Masahito Kanamura, Toshihide Kikkawa, Kenji Imanishi
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Publication number: 20140346526Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; an insulating layer formed on the second semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; and a gate electrode formed on the insulating layer. The insulating layer is formed of a material including an oxide and is formed by laminating a first insulating layer and a second insulating layer in a positioning order of the first insulating layer followed by the second insulating layer from a side of the second semiconductor layer, and an amount of hydroxyl groups included in per unit volume of the first insulating layer is less than an amount of hydroxyl groups included in per unit volume of the second insulating layer.Type: ApplicationFiled: May 19, 2014Publication date: November 27, 2014Applicant: FUJITSU LIMITEDInventor: Masahito Kanamura
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Patent number: 8895378Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.Type: GrantFiled: October 10, 2013Date of Patent: November 25, 2014Assignee: Fujitsu LimitedInventors: Masahito Kanamura, Kozo Makiyama
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Patent number: 8866157Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.Type: GrantFiled: May 23, 2013Date of Patent: October 21, 2014Assignee: Fujitsu LimitedInventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
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Patent number: 8846479Abstract: A semiconductor device includes: a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, and an electrode formed over the insulating film, wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, and the third insulating film contains a halogen.Type: GrantFiled: March 4, 2013Date of Patent: September 30, 2014Assignee: Fujitsu LimitedInventor: Masahito Kanamura