Patents by Inventor Masahito Takahashi
Masahito Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220366451Abstract: In a display apparatus, an acquisition unit acquires coordinate information associated with a fiducial marker installed in a specific area of a real space and a virtual object including advertisement information, an imaging unit images a real image and the fiducial marker, a self-position specifying unit specifies a self-position from a distance and an angle from the imaged fiducial marker, a state detecting unit detects a distance and an angle of view from the virtual point based on the self-position, a selection unit selects any virtual object existing within an angle of view from the self-position, and a display unit displays a main object of the virtual object existing within the angle of view from the self-position in such a manner that the main object is superimposed on a relative position on the real image and displays a main object and a sub object of the selected virtual object.Type: ApplicationFiled: October 15, 2020Publication date: November 17, 2022Applicant: NEC Solution Innovators, Ltd.Inventors: Wataru SAKUMA, Kohei KANAZAWA, Yutaka MORIKAWA, Hikaru NONAKA, Masahito TAKAHASHI, Takamitsu WATANABE, Keisuke SUMIDA, Yohei MIZUTANI, Yuya KIMOTO
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Publication number: 20140191533Abstract: Provided is a pillar trim (30) (a vehicle interior trim) with a main body part (32) formed in a hollow, three-dimensional structure by a thermoplastic synthetic resin. The exterior surface of the main body part (32) has a structure whereby an attachment surface (32a) attached to a vehicle structural member and a design surface (32b) inside the vehicle which are both joined together. In addition, the main body part (32) is formed of a bag-like construction that restricts the flow of internal air to the outside, and the main body part (32) distributes and absorbs impact forces from passenger during vehicle impact by using the internal pressure thereof.Type: ApplicationFiled: June 20, 2011Publication date: July 10, 2014Applicant: HOWA TEXTILE INDUSTRY CO., LTDInventor: Masahito Takahashi
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Publication number: 20060214254Abstract: To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.Type: ApplicationFiled: May 31, 2006Publication date: September 28, 2006Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
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Patent number: 7084477Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.Type: GrantFiled: June 23, 2003Date of Patent: August 1, 2006Assignees: Hitachi, Ltd., Trecenti Technologies, Inc.Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
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Patent number: 6787411Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.Type: GrantFiled: December 30, 2002Date of Patent: September 7, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi
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Patent number: 6714447Abstract: It is possible to suppress or prevent so-called write disturbance phenomenon from occurring in write-disabled non-selected memory cells in a semiconductor device, in any selected one of which data can be written electrically by means of the so-called tunneling phenomenon. In a flash memory that can disable writing of data by suppressing injection of electrons in the accumulation layer of each non-selected memory cell in which data is to be written with a writing disable voltage applied to the drain thereof before a write voltage is applied to the control gate electrode of each selected memory cell, the relationship among a writing disable voltage Vwd, a read voltage Vr applied to the drain of a selected memory cell from which data is to be read, and a punch-through withstand voltage BVds between the source and the drain of each selected memory cell is set to satisfy Vr<BVds<Vwd.Type: GrantFiled: March 1, 2002Date of Patent: March 30, 2004Assignee: Renesas Technology CorporationInventors: Akihiko Satoh, Masahito Takahashi
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Publication number: 20040058499Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.Type: ApplicationFiled: June 23, 2003Publication date: March 25, 2004Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
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Patent number: 6646303Abstract: The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film for a floating gate electrode is made thinner than a minimum processing size F, and a width taken along the gate-width direction, of an upper conductor film for the floating gate electrode, which is provided with an insulating film disposed on source and drain regions interposed therebetween, is made thicker than the minimum processing size F, whereby a reduction in the ratio of coupling between a control gate electrode and a floating gate electrode due to the scaling down of a unit cell area is restrained.Type: GrantFiled: October 10, 2001Date of Patent: November 11, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Akihiko Satoh, Masahito Takahashi, Takayuki Yoshitake
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Publication number: 20030129001Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.Type: ApplicationFiled: December 30, 2002Publication date: July 10, 2003Inventors: Teruaki Kisu, Teruo Kisu, Haruko Kisu, Kazuo Nakazato, Masahito Takahashi
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Patent number: 6501116Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.Type: GrantFiled: December 27, 2001Date of Patent: December 31, 2002Assignee: Hitachi, Ltd.Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi
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Publication number: 20020158273Abstract: The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film for a floating gate electrode is made thinner than a minimum processing size F, and a width taken along the gate-width direction, of an upper conductor film for the floating gate electrode, which is provided with an insulating film disposed on source and drain regions interposed therebetween, is made thicker than the minimum processing size F, whereby a reduction in the ratio of coupling between a control gate electrode and a floating gate electrode due to the scaling down of a unit cell area is restrained.Type: ApplicationFiled: October 10, 2001Publication date: October 31, 2002Applicant: Hitachi, Ltd.Inventors: Akihiko Satoh, Masahito Takahashi, Takayuki Yoshitake
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Publication number: 20020141240Abstract: To suppress or prevent the so-called write disturbance phenomenon from occurring in write-disabled non-selected memories in a semiconductor device provided with a plurality of memory cells, in any selected one of which data can be written electrically by means of the so-called tunneling phenomenon. In a flash memory that can disable writing of data by suppressing injection of electrons in the accumulation layer of each non-selected memory cell in which data is to be written with a writing disable voltage applied to the drain thereof before a write voltage is applied to the control gate electrode of each selected memory cell, the relationship among a writing disable voltage Vwd, a read voltage Vr applied to the drain of a selected memory cell from which data is to be read, and a punch-through withstand voltage BVds between the source and the drain of each selected memory cell is set so as to satisfy Vr<BVds<Vwd.Type: ApplicationFiled: March 1, 2002Publication date: October 3, 2002Inventors: Akihiko Satoh, Masahito Takahashi
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Publication number: 20020098639Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.Type: ApplicationFiled: December 27, 2001Publication date: July 25, 2002Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi, Teruo Kisu, Haruko Kisu
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Patent number: 6423584Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode. A hole for connecting between the two layers of the gate electrode of a first field-effect transistor used as perpheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting between the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode.Type: GrantFiled: March 20, 2001Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Patent number: 6420754Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells. A hole for connecting the two layers of the gate electrode of a first field-effect transistor used as peripheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.Type: GrantFiled: February 26, 2001Date of Patent: July 16, 2002Assignee: Hitachi, Ltd.Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Publication number: 20010024859Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.Type: ApplicationFiled: March 20, 2001Publication date: September 27, 2001Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Publication number: 20010020718Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.Type: ApplicationFiled: February 26, 2001Publication date: September 13, 2001Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Patent number: 5898621Abstract: A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvoType: GrantFiled: July 31, 1997Date of Patent: April 27, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada
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Patent number: 5677868Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cellType: GrantFiled: October 31, 1996Date of Patent: October 14, 1997Assignee: Hitachi, Ltd.Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada
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Patent number: 5598368Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cellsType: GrantFiled: May 19, 1995Date of Patent: January 28, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada