Patents by Inventor Masakatsu Nagata
Masakatsu Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7366165Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.Type: GrantFiled: February 19, 2002Date of Patent: April 29, 2008Assignee: Fujitsu LimitedInventors: Kenichi Kawarai, Masakatsu Nagata, Hiroshi Tomonaga, Naoki Matsuoka, Tsuguo Kato
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Patent number: 7227861Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.Type: GrantFiled: March 13, 2001Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Hiroshi Tomonaga, Masakatsu Nagata, Kenichi Kawarai, Naoki Matsuoka, Kenichi Okabe, Shiro Uriu
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Patent number: 7058751Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.Type: GrantFiled: August 30, 2001Date of Patent: June 6, 2006Assignee: Fujitsu LimitedInventors: Kenichi Kawarai, Hiroshi Tomonaga, Naoki Matsuoka, Masakatsu Nagata, Tsuguo Kato, Tetsuaki Wakabayashi
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Patent number: 7023865Abstract: A packet switch which can cyclically use ? scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by ? scheduler sections independently performing scheduling processes is disclosed.Type: GrantFiled: August 30, 2001Date of Patent: April 4, 2006Assignee: Fujitsu LimitedInventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Patent number: 6892452Abstract: A Dry-Film resist formed of, for example, a photosensitive film is stacked on the electroconductive material and these portions, other than a projection electrode formation area, formed on a wiring board's electrode serving as a portion of a circuit pattern are masked with a mask. After this, the wiring board is exposed to light and, after the removal of the mask, a development process is performed, thus eliminating the Dry-Film resist on the wiring board at the portion other than the projection electrode formation area. Then the electroconductive material of the wiring board is etched under an etching process to provide a projection electrode having a bump with a pointed tapering end in vertical cross-section. Finally, the wiring board is exposed to a Dry-Film resist elimination solution to remove remaining Dry-Film resist from the projection electrode. And a plating process is performed on the electroconductive material to form a plated layer and hence complete the projection electrode.Type: GrantFiled: April 26, 2001Date of Patent: May 17, 2005Assignee: DDK Ltd.Inventors: Yasuo Fukuda, Masakatsu Nagata, Shoji Iwasaki, Osamu Nakao
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Publication number: 20030147398Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.Type: ApplicationFiled: August 30, 2001Publication date: August 7, 2003Inventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Publication number: 20020122424Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.Type: ApplicationFiled: February 19, 2002Publication date: September 5, 2002Inventors: Kenichi Kawarai, Masakatsu Nagata, Hiroshi Tomonaga, Naoki Matsuoka, Tsuguo Kato
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Publication number: 20020110129Abstract: A scheduling method includes the steps of processing scheduling processes of all input lines according to a processing sequence in which a highest priority output line of a highest priority input line is processed with a first priority, in an environment in which a plurality of processing sequences have different scheduling targets among a plurality of input lines, and updating the highest priority input line and the highest priority output line of each input line for every scheduling cycle.Type: ApplicationFiled: October 9, 2001Publication date: August 15, 2002Inventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Publication number: 20020099900Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.Type: ApplicationFiled: August 31, 2001Publication date: July 25, 2002Inventors: Kenichi Kawarai, Hiroshi Tomonaga, Naoki Matsuoka, Masakatsu Nagata, Tsuguo Kato, Tetsuaki Wakabayashi
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Publication number: 20020080796Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.Type: ApplicationFiled: August 31, 2001Publication date: June 27, 2002Inventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Publication number: 20020024949Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.Type: ApplicationFiled: March 13, 2001Publication date: February 28, 2002Inventors: Hiroshi Tomonaga, Masakatsu Nagata, Kenichi Kawarai, Naoki Matsuoka, Kenichi Okabe, Shiro Uriu
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Publication number: 20010038293Abstract: A DF formed of, for example, a photosensitive film is stacked on the electroconductive material and these portions, other than a projection electrode formation area, formed on a wiring board's electrode serving as a portion of a circuit pattern are masked with a mask. After this, the wiring board is exposed to light and, after the removal of the mask, a development process is performed, thus eliminating the DF on the wiring board at the portion other than the projection electrode formation area. Then the electroconductive material of the wiring board is etched under an etching process to provide a projection electrode having a bump with a pointed tapering end in vertical cross-section. Finally, the wiring board is exposed to a DF elimination solution to remove remaining DF from the projection electrode. And a plating process is performed on the electroconductive material to form a plated layer and hence complete the projection electrode.Type: ApplicationFiled: April 26, 2001Publication date: November 8, 2001Inventors: Yasuo Fukuda, Masakatsu Nagata, Shoji Iwasaki, Osamu Nakao
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Patent number: 5694295Abstract: A heat pipe for transferring heat as the latent heat of evaporation to a radiating portion at a lower temperature by heating a heating portion of a container to evaporate a working fluid and by conveying the produced vapor to the radiating portion thereby to condense the vapor. The container is formed into a flattened hollow shape by: a flat heating portion; a radiating portion opposed at a distance to the heating portion and having a larger area than that of the heating portion; and side wall portions jointing the heating portion and the radiating portion to each other along the entire peripheral edge portions of the same.Type: GrantFiled: April 26, 1996Date of Patent: December 2, 1997Assignee: Fujikura Ltd.Inventors: Masataka Mochizuki, Motoyuki Ono, Koichi Mashiko, Yuji Saito, Masashi Hasegawa, Masakatsu Nagata