Abstract: A test pattern is supplied to the IC under test and a current corresponding to the power supply current of the IC is obtained from a current converter. A reference current reverse in polarity from the output current of the current converter is yielded from a reference current source. The output currents of the current converter and the reference current source are supplied to an integrating capacitor via first and second switches, respectively. The first and second switches are simultaneously turned ON in synchronism with the test pattern and held in the ON state in a specified phase for a specified period in one operation cycle. The voltage of the integrating capacitor immediately after turning-OFF of the first and second switches is compared with a reference voltage and the comparison result is output. After the outputting of the comparison result and before the turning-ON of the first and second switches the voltage of the integrating capacitor is reset by reset means to the reference voltage.