Abstract: A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

Abstract: Multiple parallel-job scheduling method and apparatus are provided which can improve the utilization of all processors in a system when a plurality of parallel jobs are executed concurrently. A plurality of processors constituting a computer system and each having the equal function are logically categorized into serial processors for executing a serial computing part or a parallel computing part of a parallel job and a parallel processor group consisting of multiple processors for executing the parallel computing part of the parallel job in parallel. In order that the parallel processors are shared by a plurality of parallel jobs, a synchronization range indicator is provided which can control by program whether the parallel processors are available in correspondence to the respective serial processors.

Abstract: Disclosed is a computer system containing plural processors, a shared storage shared by the plural processors, a buffer storage for storing a copy of a portion of data of the shared storage disposed in each of the plural processors, and a storage controller having a communication buffer storage disposed halfway between the buffer storage and the shared storage for storing a copy of a portion of data of the shared storage as an object for storing only an operand data of a particular instruction. This computer system can implement communication of data of the shared storage between the plural processors by using the communication buffer storage in an efficient way.

Abstract: In a disclosed embodiment of the address space control apparatus, each general-purpose register usable as a base register is associated with another general-purpose register in addition to an access register containing a segment table origin. When a general-purpose register is selected as a base register, the contents of its associated general-purpose register are read out and added to the segment table origin from the associated access register to provide an effective segment table origin. In a modification, the access registers are omitted, and the general-purpose register selected as a base register are used to select an entry in a register or register array containing segment table origins in respective entries. In other embodiments disclosed, general-purpose registers are used in different manners to enhance virtual address space control functions.