Abstract: An impedance control system is composed of a target circuit having a controllable impedance; a replica circuit having a structure identical to the target circuit; a first binary counter providing the replica circuit with a first impedance control code indicative of a counter value of the first binary counter for controlling an impedance of the replica circuit; a comparator comparing a voltage received from the replica circuit with a reference signal; a second binary counter responsive to an output signal from the comparator for being counted up or down; and a control circuit extracting upper multiple bits out of a counter value of the second binary counter, and generating a second impedance control code indicative of the upper multiple bits. The impedance of the target circuit is controlled in response to the second impedance control code.

Abstract: An impedance control system is composed of a target circuit having a controllable impedance; a replica circuit having a structure identical to the target circuit; a first binary counter providing the replica circuit with a first impedance control code indicative of a counter value of the first binary counter for controlling an impedance of the replica circuit; a comparator comparing a voltage received from the replica circuit with a reference signal; a second binary counter responsive to an output signal from the comparator for being counted up or down; and a control circuit extracting upper multiple bits out of a counter value of the second binary counter, and generating a second impedance control code indicative of the upper multiple bits. The impedance of the target circuit is controlled in response to the second impedance control code.

Abstract: An object of the present invention is to provide a terminating resistor device and a testing method, by which the resistance value of a terminating resistor circuit can be test effectively. The test procedure starts with setting a MUXSCANFF circuit which functions as a selecting circuit in scan mode for test. Then, input a test signal to the scan input and/or clock input. Thereby, a particular resistor element for one bit only is set ON. By detecting the resistance value of this resistor element that has been set ON, it is test whether the one-bit resistance element conforms to manufacturing specification. Select another one of the one-bit resistor elements in order and test each one-bit resistor element, thereby testing all resistor elements.

Abstract: An object of the present invention is to provide a terminating resistor device and a testing method, by which the resistance value of a terminating resistor circuit can be test effectively. The test procedure starts with setting a MUXSCANFF circuit which functions as a selecting circuit in scan mode for test. Then, input a test signal to the scan input and/or clock input. Thereby, a particular resistor element for one bit only is set ON. By detecting the resistance value of this resistor element that has been set ON, it is test whether the one-bit resistance element conforms to manufacturing specification. Select another one of the one-bit resistor elements in order and test each one-bit resistor element, thereby testing all resistor elements.

Abstract: An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.

Abstract: An output buffer circuit having a function of accomplishing preemphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.

Abstract: Such a configuration is provided that a clamp circuit and a level shifting circuit are connected to an output of a source-follower circuit connected to a positive power supply, to apply a negative power supply via a transmission line and a terminating resistor to an output end of the level shifting circuit. With this, a CMOS-level logic signal input to the source-follower circuit is shifted in level toward a level of the negative power supply side. In this case, that signal is clamped by the clamp circuit, during which thus level-shifted signal is shifted in level by the level shifting circuit further toward the negative power supply side, thus permitting an ECL-level signal to pass through the transmission line and appear across the terminating resistor in order to be subsequently applied to an ECL logic circuit.

Abstract: A circuit for converting a negative ECL level to a positive CMOS level is formed by a level conversion circuit input terminal 4 for inputting a negative ECL level, a level shifter 5, one end of which is connected to the input terminal 4, a load 6 of the level shifter 5, one end of which is connected to the level shifter 5 and the other end of which is connected to a positive power supply VDD, and a positive ECL-CMOS level converter 7 for comparing a voltage that is level shifted by the level shifter 5 with a reference voltage Vref and converting to a CMOS level.

Abstract: A 90° phase shift circuit receives an input signal to generate a Q-signal and an I-signal having a phase difference of 90° therebetween. The 90° phase shift circuit has a CR-type high-pass filter having a variable capacitor and fixed resistor, a CR-type low-pass filter having a variable capacitor and a fixed resistor, and a level comparator for comparing the amplitudes of both the outputs from the filters to feed-back a control signal for controlling the cut-off frequencies of both the filters.

Abstract: For time division multiplexing N bit-parallel circuit input signals at a high bit rate such as higher than 2.4 Gb/s, where N represents a predetermined integer greater than one, a multiplexer circuit comprises an N-stage shift register (11) for shifting a signal pulse through first to N-th dual output D F/F's (11(1)-11(N)) to produce N master and slave output signals as N stage output signals, N two-input NAND gates (15(1)-15(N)) supplied with the N bit parallel circuit input signals and the N master output signals to produce N gate output signals, an N-input NAND gate (17) multiplexing the N gate output signals into a single gate output signal, and a retiming D F/F (19) for retiming the single gate output signal into a bit-serial circuit output signal. The N slave output signals are delivered respectively to the dual output D F/F's of next stages.

Abstract: In a semiconductor device, a first resistor is connected between the base and collector of a dummy bipolar transisitor, a second resistor is connected between the base and emitter of the dummy bipolar transistor, and a third resistor is connected to the collector of the dummy bipolar transistor. A first pad and a second pad are connected to the base and emitter, respectively, of the dummy bipolar transistor. A third pad is connected to the third resistor. A fourth pad is connected to the collector of the dummy bipolar transistor.

Abstract: An emitter-coupled logic circuit includes a differential pair of transistors and an emitter follower output stage. A load inductor is connected to one of the differential transistors and a load resistor is connected to the other one of the differential transistors. The emitter follower output stage having an input node connected to the load resistor and an output node is connected to a constant current source formed by a current source transistor and an inductor which is AC-coupled to the load inductor by a mutual induction effect. The pull-up and pull-down delay times of the emitter coupled logic circuit can be reduced in a wide range from a light load to a heavy load.

Abstract: A semiconductor integrated circuit device includes an internal circuit, input and output signal pads, a power source pad and a plurality of ground pads, a ground pattern, and a power source pattern. The internal circuit is formed in a predetermined region of a semiconductor substrate. The input and output signal pads are arranged on a semiconductor substrate surface and connected to the internal circuit. The power source pad and the plurality of ground pads are arranged on the semiconductor substrate surface and supply a power source to the internal circuit. The ground pattern is arranged in a region of the surface of the semiconductor substrate different from the region in which the internal circuit is formed, and the ground pattern connects the plurality of ground pads to each other. The power source pattern is formed below the ground pattern through an insulating interlayer and connected to the power source pad.