Patents by Inventor Masakazu Muraguchi

Masakazu Muraguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152468
    Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 19, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kunihiro Tsubomi, Tetsuo Endoh, Masakazu Muraguchi
  • Patent number: 11054463
    Abstract: A method and a system for measuring the thermal stability factor of a magnetic tunnel junction device, a semiconductor integrated circuit, and a production management method for the semiconductor integrated circuit, capable of measuring the thermal stability factors of individual devices in a relatively short period of time and quickly performing quality control during material development and at a production site. A meter measures change in resistance value of an evaluation MTJ for a predetermined period while causing a predetermined current to flow into the evaluation MTJ maintained at a predetermined temperature. An analyzer calculates a time constant in which a low-resistance state is maintained and a time constant in which a high-resistance state is maintained from the measured change in resistance value. A thermal stability factor of the evaluation MTJ is calculated on the basis of the calculated time constants and the predetermined current flowing into the evaluation MTJ.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 6, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kenchi Ito, Tetsuo Endoh, Hideo Sato, Takashi Saito, Masakazu Muraguchi, Hideo Ohno
  • Publication number: 20190219633
    Abstract: A method and a system for measuring the thermal stability factor of a magnetic tunnel junction device, a semiconductor integrated circuit, and a production management method for the semiconductor integrated circuit, capable of measuring the thermal stability factors of individual devices in a relatively short period of time and quickly performing quality control during material development and at a production site. A meter measures change in resistance value of an evaluation MTJ for a predetermined period while causing a predetermined current to flow into the evaluation MTJ maintained at a predetermined temperature. An analyzer calculates a time constant in which a low-resistance state is maintained and a time constant in which a high-resistance state is maintained from the measured change in resistance value. A thermal stability factor of the evaluation MTJ is calculated on the basis of the calculated time constants and the predetermined current flowing into the evaluation MTJ.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 18, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Kenchi ITO, Tetsuo ENDOH, Hideo SATO, Takashi SAITO, Masakazu MURAGUCHI, Hideo OHNO
  • Publication number: 20190115430
    Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.
    Type: Application
    Filed: March 30, 2017
    Publication date: April 18, 2019
    Inventors: Kunihiro Tsubomi, Tetsuo Endoh, Masakazu Muraguchi