Patents by Inventor Masakazu Urade

Masakazu Urade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060259719
    Abstract: A control terminal is provided which is capable of improving a usage efficiency of a main memory means. An elapsed time measuring unit measures an elapsed time (unused time) since a control program of a device stored in the a main memory (main memory means) has been lastly used in a computer (control terminal). Then, the computer automatically unloads a control program having an elapsed time equal to or greater than a predetermined threshold value from the main memory.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 16, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Hirano, Masakazu Urade, Mitsuya Nakahara
  • Publication number: 20050182748
    Abstract: A file system control apparatus, which exclusively shares a recording device upon executing first and second file systems, is provided with a file system controller, which controls in such a manner that, even when, during access execution of the first file system to a recording device, an access execution request to the recording device is given from the second file system that is different from the first file system, the access execution of the second file system is not delayed by the access execution of the first file system.
    Type: Application
    Filed: January 24, 2005
    Publication date: August 18, 2005
    Inventors: Tomohiro Hirata, Masakazu Urade, Sachiko Maeda, Tomoko Uenishi
  • Patent number: 6529988
    Abstract: Disclosed is an apparatus and method for transferring data from a directly from peripheral computer device to a computer via a universal serial bus. The disclosed method and apparatus can also compress the transferred data. The apparatus can include a Serial Interface Engine (SIE) connected with the computer and having a latch and a First-In-First-Out memory (FIFO) connected to the latch of the SIE. The FIFO temporarily stores data from the peripheral computer device and transfers the data to the latch of the SIE. A read input of the latch is driven at a first clock frequency and an output of the FIFO is driven at a second clock frequency. The second clock frequency is at least intermittently higher than the first clock frequency. Thus, a portion of the data placed on the output of the FIFO at the second clock frequency is not read into the latch. This allows data to be compressed as it is transferred from the FIFO to the SIE.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electrical Industrial
    Inventors: Hiroto Yoshikawa, Masakazu Urade
  • Patent number: 6272644
    Abstract: A method of controlling a USB hub by a microcontroller, comprising the steps of sending a suspend request to the microcontroller from the USB hub; sending a stop clock request from the microcontroller to the USB hub in response to the suspend request; and stopping the USB hub controller clock in response to the suspend request; entry into a powersave mode by the microcontroller in response to the suspend request.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: August 7, 2001
    Assignee: Matsushita Electrical Industrial Co., Ltd.
    Inventors: Masakazu Urade, Eskandar Afshar, Liang Lin
  • Patent number: 5483289
    Abstract: A circuit and method of data slicing a television signal comprises: an extractor 2 for extracting a specific component from the television signal of analog form; a slicer 3 for slicing the specific component of the television signal produced by the extractor 2 and converting it to its digital form; a decoder 4 for decoding an output of the slicer 3 for display; an initial value storage 10 for storing an initial value of the slice level; slice level controllers 7 and 8 for varying the initial slice level at a predetermined rate; a signal detector 11 for examining whether or not the digitized specific component from the slicer 3 is a desired multiplex signal; a temporary slice level memory 13 for storing the upper and lower levels of the desired multiplex signal detected by the signal detector 11; a calculator 9 for calculating an optimum value of the slice level from the upper and lower levels of the multiplex signal stored in the temporary slice level memory 13; a slice level storage 6 for storing the optimum
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: January 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakazu Urade, Hisao Kobayashi, Yukihiro Yagi, Katsuhiko Hashimoto, Sachiko Nishii