Abstract: A packet processing apparatus sets, for each TS as a gate state of each of a first gate and a second gate, a priority state, a normal state, and a mixed state and sets a predetermined TS associated with a cyclic pattern of the first packet to the priority or the mixed state. The apparatus allocates, when an amount of output delay of the first packet that is in the mixed state in the predetermined TS is within an allowable amount, the first packet and the second packet to the predetermined TS. The apparatus sets output timing of the first packet allocated in the predetermined TS to the priority state and sets output timing of the second packet allocated in the predetermined TS to the normal state.

Abstract: A packet processing device includes a memory, and circuitry coupled the memory and configured to perform: sampling received packets at a predetermined interval, detecting a plurality of bursts in which received packets are continuously detected by the sampling, calculating, for each of the plurality of bursts detected, a front edge period based on the received packet detected first among the bursts, calculating, for each of the plurality of bursts detected, a rear edge period based on the received packet detected last among the bursts, deciding the longer period between the front edge period and the rear edge period as a burst period, and controlling transfer of the received packets based on the decided burst period.

Abstract: A packet processing apparatus sets, for each TS as a gate state of each of a first gate and a second gate, a priority state, a normal state, and a mixed state and sets a predetermined TS associated with a cyclic pattern of the first packet to the priority or the mixed state. The apparatus allocates, when an amount of output delay of the first packet that is in the mixed state in the predetermined TS is within an allowable amount, the first packet and the second packet to the predetermined TS. The apparatus sets output timing of the first packet allocated in the predetermined TS to the priority state and sets output timing of the second packet allocated in the predetermined TS to the normal state.

Abstract: A packet processing device includes a memory, and circuitry coupled the memory and configured to perform: sampling received packets at a predetermined interval, detecting a plurality of bursts in which received packets are continuously detected by the sampling, calculating, for each of the plurality of bursts detected, a front edge period based on the received packet detected first among the bursts, calculating, for each of the plurality of bursts detected, a rear edge period based on the received packet detected last among the bursts, deciding the longer period between the front edge period and the rear edge period as a burst period, and controlling transfer of the received packets based on the decided burst period.

Abstract: An electronic component includes an inner electrode inside of a main body and exposed at a surface of the main body, and an outer electrode on a surface of the main body and electrically connected to the inner electrode, wherein a plurality of recesses are provided in a surface of the outer electrode, and each of the plurality of recesses includes a portion in which a diameter of an opening of the recess gradually decreases toward an opening side of the recess.

Abstract: A switch include a memory that stores tree data used for a tree search in which a search for a forwarding destination of received data is made by a tree search system and cache data used for a cache search in which a search for the forwarding destination is made by a cache search system, and a controller that concurrently carries out the tree search and the cache search based on forwarding control identification information included in the received data and decides the forwarding destination of the received data in accordance with a search result that is obtained earlier in search results of the tree search and the cache search.

Abstract: An electronic component includes an inner electrode inside of a main body and exposed at a surface of the main body, and an outer electrode on a surface of the main body and electrically connected to the inner electrode, wherein a plurality of recesses are provided in a surface of the outer electrode, and each of the plurality of recesses includes a portion in which a diameter of an opening of the recess gradually decreases toward an opening side of the recess.

Abstract: A control apparatus including: a memory, and a processor coupled to the memory and the processor configured to: retain first packets in the memory, output the retained first packets to a processing apparatus including a packet processor, receive second packets processed by the packet processor from the processing apparatus, and control outputting of the retained first packets based on the outputted first packets and the received second packets.

Abstract: A data processing system includes: a plurality of processing units configured to execute processing for a plurality of packets; and a processor configured to transmit the plurality of packets to the plurality of processing units. The processor is configured to calculate processing cost total value for each of the plurality of processing units by adding the value of the processing cost of each of the transmitted packets each time the packet is transmitted to any one of the plurality of processing units, based on processing cost information indicating a value of a processing cost of each of the plurality of packets, and subtracting the value of the processing cost of each of the plurality of received packets, select a transmission destination of a first packet, by comparing the processing cost total values of the plurality of processing units, and transmit the first packet to the selected processing unit.

Abstract: A packet relay device includes: a first buffer configured to store a packet; and a processor coupled to the first buffer and configured to: calculate a delay time for reading from the first buffer based on a packet length and a packet interval of the packet which is inputted to the first buffer, and delay the packet according to the calculated delay time, the packet being read from the first buffer.

Abstract: A communication device includes: first and second memories configured to store first and second packets in first and second queues, respectively; a processor configured to: select a packet to be transmitted by selecting the first packet in priority to the second packet, read the selected packet from the first or second queue, and detect the first packet stored in the first queue during reading of the second packet from the second queue; and a third memory configured to hold copied data relating to the second packet, wherein when detecting the first packet, the processor is configured to cause an internal or external part of the communication device to discard the currently read second packet, read the first packet stored in the first queue, and read the copied data from the third memory after completion of the reading of the first packet.

Abstract: A ceramic electronic component includes a ceramic base, first and second internal electrodes, and first and second external electrodes. The first external electrode is disposed at a first end portion of a first major surface in the longitudinal direction. The second external electrode is disposed at a second end portion of the first major surface in the longitudinal direction. A portion of each of the first and second external electrodes is opposed in the thickness direction to a region where the first and second internal electrodes are opposed to each other in the thickness direction. A condition ( 1/10)t0?t1 ?(?)t0 is satisfied, where to is the thickness of each of the first and second external electrodes and t1 is the thickness of a portion in which each of the first and second external electrodes is embedded in the first major surface.

Abstract: A communication device includes a memory to store data and a processor to receive data, to convert the received data and a same data of the received data among the stored data into a predetermined format, and to transmit data resulting from the data conversion.

Abstract: A relaying apparatus includes a memory that stores a program including a procedure, and a processor that executes the program including the procedure, wherein the procedure includes delaying, when received packet data includes a synchronization message for any one of a frequency synchronization and a time synchronization, a transmission of the received packet data so that a period of time for a relaying process attains a given value.

Abstract: A liquid level detector is provided. A resistance plate has a plurality of conductive segments. A float vertically moves according to change of a liquid level to be measured. A float arm has one end attached to the float and the other end rotatably supported to rotate according to the vertical movement of the float. Contact points slide on the conductive segments with the rotation of the float arm according to the liquid level. The conductive segments are formed of a glass-sintered metallic body made of glass and gold alloy material containing a gold (Au) content equal to or greater than 18% by mass and less than 40% by mass. The contact points are formed of a gold alloy material containing a gold (Au) content equal to or greater than 32.5% by mass and less than 77% by mass.

Abstract: A data block output apparatus includes a first queue that stores data blocks of first traffic; a second queue that stores data blocks of second traffic and is read preferentially over the first queue; a monitoring unit that monitors for occurrence of data blocks read out of the second queue after reading of a data block from the first queue is completed; and a control unit that controls a data block interval between completion of reading of one data block in the first traffic and a start of reading of a next data block in the first traffic when occurrence frequency of the data blocks read out of the second queue after the reading of one data block from the first queue is completed is equal to or higher than a predetermined value.

Abstract: A packet relay device includes: a first buffer configured to store a packet; and a processor coupled to the first buffer and configured to: calculate a delay time for reading from the first buffer based on a packet length and a packet interval of the packet which is inputted to the first buffer, and delay the packet according to the calculated delay time, the packet being read from the first buffer.

Abstract: A ceramic electronic component includes a ceramic base, first and second internal electrodes, and first and second external electrodes. The first external electrode is disposed at a first end portion of a first major surface in the longitudinal direction. The second external electrode is disposed at a second end portion of the first major surface in the longitudinal direction. A portion of each of the first and second external electrodes is opposed in the thickness direction to a region where the first and second internal electrodes are opposed to each other in the thickness direction. A condition ( 1/10)t0?t1 ?(?)t0 is satisfied, where to is the thickness of each of the first and second external electrodes and t1 is the thickness of a portion in which each of the first and second external electrodes is embedded in the first major surface.

Abstract: A ceramic electronic component includes a ceramic base, first and second internal electrodes, and first and second external electrodes. The first external electrode is disposed at a first end portion of a first major surface in the longitudinal direction. The second external electrode is disposed at a second end portion of the first major surface in the longitudinal direction. A portion of each of the first and second external electrodes is opposed in the thickness direction to a region where the first and second internal electrodes are opposed to each other in the thickness direction. A condition ( 1/10)t0?t1?(?)t0 is satisfied, where t0 is the thickness of each of the first and second external electrodes and t1 is the thickness of a portion in which each of the first and second external electrodes is embedded in the first major surface.

Abstract: A micro fluidic device comprises a micro channel in which a plurality of fluids form laminar flows and are supplied, wherein an inner wall of the micro channel comprise a protruding part that is substantially parallel to the flows of the fluids and protrudes in directions substantially vertical to interfaces formed by the plurality of fluids.