Abstract: A power switch circuit that ensures suppression of an increase in a transient current. The power switch circuit includes a first transistor, which generates an output voltage in response to a control signal, and a time difference generation circuit, which delays the control signal by performing a logical process with the output voltage of the first transistor and the control signal.

Abstract: A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the power source voltage line and the ground line, including at least two second MOS transistors coupled in series. The gate length and the gate width of the first MOS transistor are adjusted so that the first MOS transistor has a gate area allowing a first characteristic variation of the first MOS transistor to be substantially equal to a second characteristic variation of the second MOS transistor.

Abstract: A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the power source voltage line and the ground line, including at least two second MOS transistors coupled in series. The gate length and the gate width of the first MOS transistor are adjusted so that the first MOS transistor has a gate area allowing a first characteristic variation of the first MOS transistor to be substantially equal to a second characteristic variation of the second MOS transistor.

Abstract: A power switch circuit that ensures suppression of an increase in a transient current. The power switch circuit includes a first transistor, which generates an output voltage in response to a control signal, and a time difference generation circuit, which delays the control signal by performing a logical process with the output voltage of the first transistor and the control signal.

Abstract: The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a higher degree of freedom of wirings. The connection terminals 2 and 3 of the fundamental cell 1 are terminals for supplying the power source voltage VDD and ground potential VSS to the N and P type wells. The terminals may be defined as a contact structure between a metal layer and N and P type well areas, and alternatively defined as stacked VIA structure for multilayered metal wiring layers and N and P type well areas if desired in correspondence with the manufacturing process used for manufacturing the semiconductor integrated circuit device implementing the fundamental cell 1. The fundamental cell 1 has neither the connection terminals 2 and 3, nor the power source voltage VDD and ground potential VSS to those two PMOS and NMOS transistors.

Abstract: A decoupling capacitor includes a first MOS transistor having a first conductivity type. The first MOS transistor functions as a resistor element due to an on-resistance between its source and drain. The source is connected to first power supply wiring. The decoupling capacity further includes a second MOS transistor having a second conductivity type. The second MOS transistor is connected to second power supply wiring. The second MOS transistor functions as a capacitor element and has a gate length greater than that of the first MOS transistor.

Abstract: A master-slave circuit that includes a master circuit having input data stored therein, a storage unit for receiving the input data in response to receiving a sleep mode setting signal that sets a sleep mode, and for storing the input data, and a first control unit for interrupting the supply of a power supply voltage to the master circuit after the input data is stored in the storage unit.

Abstract: A unit cell of a semiconductor integrated circuit capable of improving wiring efficiency in layout of a functional circuit block or the like using a unit cell, and a wiring method and wiring program using the unit cell are provided. In a unit cell, auxiliary power wiring regions are formed with reference to grids that exist from a cell edge every basic cell width in the X-direction. Input signal terminals and an output signal terminal are each arranged so as to include at least one wiring connecting portion outside the auxiliary power wiring regions. This makes it possible to wire wiring other than signal wiring in the auxiliary power wiring region. When a functional circuit block is constructed by arranging unit cells in a matrix, auxiliary power wiring regions are formed at a pitch of the basic cell width, through the functional circuit block in the Y-direction.

Abstract: A transistor layout including a diffusion region and a gate line. The gate line intersects part of the diffusion region in an overlapping manner. The layout includes an L-shaped bent portion included in the diffusion region. An auxiliary pattern is included in the diffusion region opposite to the L-shaped bent portion so that the gate line is located between the L-shaped bent portion and the auxiliary pattern. The auxiliary pattern and the L-shaped bent portion are spaced from the gate line by the same distance.

Abstract: A decoupling capacitor includes a first MOS transistor having a first conductivity type. The first MOS transistor functions as a resistor element due to an on-resistance between its source and drain. The source is connected to first power supply wiring. The decoupling capacity further includes a second MOS transistor having a second conductivity type. The second MOS transistor is connected to second power supply wiring. The second MOS transistor functions as a capacitor element and has a gate length greater than that of the first MOS transistor.

Abstract: A unit cell of a semiconductor integrated circuit capable of improving wiring efficiency in layout of a functional circuit block or the like using a unit cell, and a wiring method and wiring program using the unit cell are provided. In a unit cell, auxiliary power wiring regions are formed with reference to grids that exist from a cell edge every basic cell width in the X-direction. Input signal terminals and an output signal terminal are each arranged so as to include at least one wiring connecting portion outside the auxiliary power wiring regions. This makes it possible to wire wiring other than signal wiring in the auxiliary power wiring region. When a functional circuit block is constructed by arranging unit cells in a matrix, auxiliary power wiring regions are formed at a pitch of the basic cell width, through the functional circuit block in the Y-direction.

Abstract: A selector circuit precisely outputs a signal selected from a plurality of signals. A latch circuit unit generates an internal selection control signal for controlling a selection operation of a selector circuit unit. When the levels of first and second data input signals do not match each other, the selector circuit unit maintains its selected state and does not perform a selecting operation based on the selection signal until the levels of the signals match each other in accordance with the internal selection control signal.

Abstract: A transistor layout including a diffusion region and a gate line. The gate line intersects part of the diffusion region in an overlapping manner. The layout includes an L-shaped bent portion included in the diffusion region. An auxiliary pattern is included in the diffusion region opposite to the L-shaped bent portion so that the gate line is located between the L-shaped bent portion and the auxiliary pattern. The auxiliary pattern and the L-shaped bent portion are spaced from the gate line by the same distance.

Abstract: This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device. The present invention further provides an apparatus comprising a processor configured to carry out the inventive method. The apparatus of the present invention may include a cell library in which the auxiliary cells are registered and dummy cells are utilized. The present invention additionally provides a computer readable storage medium, containing a program code instructed to perform the method of the present invention.

Abstract: A selector circuit precisely outputs a signal selected from a plurality of signals. A latch circuit unit generates an internal selection control signal for controlling a selection operation of a selector circuit unit. When the levels of first and second data input signals do not match each other, the selector circuit unit maintains its selected state and does not perform a selecting operation based on the selection signal until the levels of the signals match each other in accordance with the internal selection control signal.

Abstract: The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a higher degree of freedom of wirings. The connection terminals 2 and 3 of the fundamental cell 1 are terminals for supplying the power source voltage VDD and ground potential VSS to the N and P type wells. The terminals may be defined as a contact structure between a metal layer and N and P type well areas, and alternatively defined as stacked VIA structure for multilayered metal wiring layers and N and P type well areas if desired in correspondence with the manufacturing process used for manufacturing the semiconductor integrated circuit device implementing the fundamental cell 1. The fundamental cell 1 has neither the connection terminals 2 and 3, nor the power source voltage VDD and ground potential VSS to those two PMOS and NMOS transistors.

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Abstract: The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a higher degree of freedom of wirings. The connection terminals 2 and 3 of the fundamental cell 1 are terminals for supplying the power source voltage VDD and ground potential VSS to the N and P type wells. The terminals may be defined as a contact structure between a metal layer and N and P type well areas, and alternatively defined as stacked VIA structure for multilayered metal wiring layers and N and P type well areas if desired in correspondence with the manufacturing process used for manufacturing the semiconductor integrated circuit device implementing the fundamental cell 1. The fundamental cell 1 has neither the connection terminals 2 and 3, nor the power source voltage VDD and ground potential VSS to those two PMOS and NMOS transistors.

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Abstract: This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device. The present invention further provides an apparatus comprising a processor configured to carry out the inventive method. The apparatus of the present invention may include a cell library in which the auxiliary cells are registered and dummy cells are utilized. The present invention additionally provides a computer readable storage medium, containing a program code instructed to perform the method of the present invention.