Patents by Inventor Masaki Kuramae

Masaki Kuramae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178064
    Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Application
    Filed: November 30, 2023
    Publication date: May 30, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru SOMA, Masahiro SHIMBO, Masaki KURAMAE, Kouhei UCHIDA
  • Patent number: 11876018
    Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: January 16, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru Soma, Masahiro Shimbo, Masaki Kuramae, Kouhei Uchida
  • Publication number: 20210090953
    Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru SOMA, Masahiro SHIMBO, Masaki KURAMAE, Kouhei UCHIDA
  • Patent number: 10892188
    Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru Soma, Masahiro Shimbo, Masaki Kuramae, Kouhei Uchida
  • Publication number: 20200395245
    Abstract: Systems and methods include semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 17, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru SOMA, Masahiro SHIMBO, Masaki KURAMAE, Kouhei UCHIDA
  • Patent number: 6455387
    Abstract: There are contained the steps of forming an undoped or low impurity concentration amorphous silicon film to project from an upper surface of a first insulating film, introducing selectively impurity into an uppermost surface of the amorphous silicon film to form the uppermost surface of the amorphous silicon film as a high concentration impurity region, forming hemispherical grained silicon on the uppermost surface of the amorphous silicon film at a first density and on a side surface at a second density higher than the first density by exposing the amorphous silicon film to a silicon compound gas and then annealing the amorphous silicon film in a low pressure atmosphere, and introducing the impurity into the hemispherical grained silicon and the amorphous silicon film. Accordingly, a semiconductor device having a capacitor, in which a cylindrical storage electrode from an upper surface of which silicon projections are difficult to come off is formed, can be provided.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: September 24, 2002
    Assignee: Fujitsu Limited
    Inventor: Masaki Kuramae
  • Publication number: 20020004275
    Abstract: There are contained the steps of forming an undoped or low impurity concentration amorphous silicon film to project from an upper surface of a first insulating film, introducing selectively impurity into an uppermost surface of the amorphous silicon film to form the uppermost surface of the amorphous silicon film as a high concentration impurity region, forming hemispherical grained silicon on the uppermost surface of the amorphous silicon film at a first density and on a side surface at a second density higher than the first density by exposing the amorphous silicon film to a silicon compound gas and then annealing the amorphous silicon film in a low pressure atmosphere, and introducing the impurity into the hemispherical grained silicon and the amorphous silicon film. Accordingly, a semiconductor device having a capacitor, in which a cylindrical storage electrode from an upper surface of which silicon projections are difficult to come off is formed, can be provided.
    Type: Application
    Filed: December 13, 2000
    Publication date: January 10, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Masaki Kuramae
  • Patent number: 6300217
    Abstract: A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: October 9, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaki Kuramae, Fumitake Mieno
  • Patent number: 5843829
    Abstract: A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: December 1, 1998
    Assignees: Fujitsu Limited, VLSI Limited
    Inventors: Masaki Kuramae, Fumitake Mieno