Patents by Inventor Masaki Nishimoto

Masaki Nishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of determining chicken embryonic stem cells
    Patent number: 8198082
    Abstract: A chicken embryonic stem cell is established, which stably has pluripotency and an ability of being differentiated into a germ cell. For evaluating on whether or not the chicken embryonic stem cell can be applied to genetic modification technique, detection is made on a protein which serves as an indicator of the ability of being differentiated into a germ cell. This provides (i) a chicken embryonic stem cell applicable to genetic modification technique and (ii) a method for evaluation of the chicken embryonic stem cell.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 12, 2012
    Assignees: Hiroshima University, Hiroshima Industrial Promotion Organization
    Inventors: Hiroyuki Horiuchi, Haruo Matsuda, Shuichi Furusawa, Mikiharu Nakano, Yusuke Yamashita, Masaki Nishimoto
  • CHICKEN EMBRYONIC STEM CELL AND METHOD FOR EVALUATION THEREOF
    Publication number: 20100205684
    Abstract: A chicken embryonic stem cell is established, which stably has pluripotency and an ability of being differentiated into a germ cell. For evaluating on whether or not the chicken embryonic stem cell can be applied to genetic modification technique, detection is made on a protein which serves as an indicator of the ability of being differentiated into a germ cell. This provides (i) a chicken embryonic stem cell applicable to genetic modification technique and (ii) a method for evaluation of the chicken embryonic stem cell.
    Type: Application
    Filed: March 26, 2008
    Publication date: August 12, 2010
    Inventors: Hiroyuki Horiuchi, Haruo Matsuda, Shuichi Furusawa, Mikiharu Nakano, Yusuke Yamashita, Masaki Nishimoto
  • Semiconductor memory device which can be tested while selecting word lines successively at high speed
    Patent number: 5943280
    Abstract: When a special operation mode is instructed, a test oscillation circuit operating at a cycle shorter than a refresh oscillation circuit specifying the cycle of self refresh is activated according to an external row address strobe signal. The internal row address strobe signal is provided to row related control circuitry via a selector. An internal row address strobe signal can be rendered active at a cycle shorter than the cycle of the external row address strobe signal, to carry out row selection. A row is selected at a cycle shorter than the transition cycle of an external signal.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 24, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukihiro Tsukamoto, Koji Kimura, Masaki Nishimoto, Masayuki Kasamoto, Naotaka Okada, Kazuhisa Uetsuki, Masakatsu Murakami, Shigekazu Aoki, Zengcheng Tian, Shin Sekiya, Akihiro Shirai
  • Semiconductor memory device having a write per bit function in page mode
    Patent number: 5315560
    Abstract: A semiconductor memory device is provided with a plurality of input circuits each having a mask information generating circuit to enable bit writing in page mode. The mask information generating circuit generates mask information from a mask control signal supplied from a mask control circuit, mask data supplied from a mask data input buffer circuit, an internal signal and a special function signal. The mask information generating circuit controls the mask information, depending on the state of the special function signal at the fall of an external column address strobe signal such that the mask information may change on each column address strobe cycle.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: May 24, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaki Nishimoto, Junko Matsumoto
  • Semiconductor memory device including address transition detecting circuit
    Patent number: 5307324
    Abstract: A transistor is provided for taking written data between a data bus line and a latch circuit in a main amplifier circuit. The gate of the transistor is supplied with a write control signal generated by a write control circuit in writing operation.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: April 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masaki Nishimoto