Patents by Inventor Masaki Okamoto

Masaki Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240163555
    Abstract: An image processing device is disclosed that includes an image acquisition unit configured to acquire a captured image captured by an imaging device fixed to a moving object; a behavior data acquisition unit configured to acquire behavior data indicating behavior of the moving object when moving; a determination unit configured to determine whether or not the captured image includes scenery outside the moving object; and an image processing unit configured to, when the captured image is determined to include the scenery outside the moving object, perform shake correction processing on the captured image based on the behavior data acquired by the behavior data acquisition unit so as to cancel the shaking of the captured image due to the behavior.
    Type: Application
    Filed: March 18, 2021
    Publication date: May 16, 2024
    Applicant: Nissan Motor Co., Ltd.
    Inventors: Jun Kasai, Hirofumi Inoue, Yu Shikoda, Masaki Okamoto, Takehito Teraguchi, Fangge Chen
  • Patent number: 11948833
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: April 2, 2024
    Assignee: Sony Group Corporation
    Inventor: Masaki Okamoto
  • Publication number: 20240091641
    Abstract: Methods and apparatus provide for acquiring position information about a head-mounted display; performing information processing using the position information about the head-mounted display; generating and outputting data of an image to be displayed as a result of the information processing; and generating and outputting data of an image of a user guide indicating position information about a user in a real space using the position information about the head-mounted display, where the image of the user guide represents a state of the real space in which the user is physically located, as viewed obliquely.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Shoichi Ikenoue, Tatsuo Tsuchie, Tetsugo Inada, Masaki Uchida, Hirofumi Okamoto
  • Publication number: 20240055465
    Abstract: A highly functional photoelectric conversion element is provided.
    Type: Application
    Filed: December 14, 2021
    Publication date: February 15, 2024
    Inventors: Kenichi MURATA, Masahiro JOEI, Shintarou HIRATA, Shingo TAKAHASHI, Yoshiyuki OHBA, Takashi KOJIMA, Tomiyuki YUKAWA, Yoshifumi ZAIZEN, Tomohiro SUGIYAMA, Masaki OKAMOTO, Takuya MASUNAGA, Yuki KAWAHARA
  • Publication number: 20240006448
    Abstract: Provided is an imaging device including: a first semiconductor substrate provided with a photoelectric conversion element, a second semiconductor substrate stacked on the first semiconductor substrate with an interlayer insulating film interposed therebetween and provided with a pixel circuit that reads out charges generated in the photoelectric conversion element as a pixel signal, and a via that penetrates the interlayer insulating film and electrically connects a first surface of the first semiconductor substrate facing the second semiconductor substrate and at least a part of a second surface of the second semiconductor substrate facing the first surface.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 4, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeya MOCHIZUKI, Keiichi NAKAZAWA, Shinichi YOSHIDA, Kenya NISHIO, Nobutoshi FUJII, Suguru SAITO, Masaki OKAMOTO, Ryosuke KAMATANI, Yuichi YAMAMOTO, Kazutaka IZUKASHI, Yuki MIYANAMI, Hirotaka YOSHIOKA, Hiroshi HORIKOSHI, Takuya KUROTORI, Shunsuke FURUSE, Takayoshi HONDA
  • Publication number: 20230121586
    Abstract: A sound data processing device includes: a sound data acquisition unit configured to acquire first sound data that is data about a sound whose sound image is localized in a cabin of a vehicle; an object specifying unit configured to specify an attention object that is an object to which an occupant of the vehicle directs attention; a sound data processing unit configured to generate second sound data that is data about the sound for which a sound relating to the attention object is emphasized in comparison with the first sound data; and a sound data output unit configured to output the second sound data to an output device that outputs a sound to the occupant.
    Type: Application
    Filed: March 25, 2020
    Publication date: April 20, 2023
    Applicant: Nissan Motor Co., Ltd.
    Inventors: Shota Ohkubo, Hirofumi Inoue, Masaki Okamoto, Jo Nishiyama, Jun Kasai, Tahehito Teraguchi, Yu Shikoda, Fangge Chen
  • Patent number: 11557573
    Abstract: There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 17, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Publication number: 20220278160
    Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 1, 2022
    Inventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE
  • Patent number: 11289525
    Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 29, 2022
    Assignee: Sony Corporation
    Inventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
  • Publication number: 20220044962
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Application
    Filed: October 22, 2021
    Publication date: February 10, 2022
    Applicant: Sony Group Corporation
    Inventor: Masaki Okamoto
  • Patent number: 11177161
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 16, 2021
    Assignee: SONY CORPORATION
    Inventor: Masaki Okamoto
  • Publication number: 20210272933
    Abstract: There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Applicant: Sony Group Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Patent number: 11063020
    Abstract: There is provided a semiconductor device a method for manufacturing a semiconductor device, and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 13, 2021
    Assignee: SONY CORPORATION
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Publication number: 20200273745
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Applicant: Sony Corporation
    Inventor: Masaki Okamoto
  • Patent number: 10690814
    Abstract: Influence of chipping in case of dicing a plurality of stacked substrates is reduced. Provided is a semiconductor device where a substrate, in which a groove surrounding a pattern configured with a predetermined circuit or part is formed, is stacked. The present technology can be applied to, for example, a stacked lens structure where through-holes are formed in each substrate and lenses are disposed in inner sides of the through-holes, a camera module where a stacked lens structure and a light-receiving device are incorporated, a solid-state imaging device where a pixel substrate and a control substrate are stacked, and the like.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: June 23, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshiaki Shiraiwa, Masaki Okamoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Minoru Ishida
  • Patent number: 10658229
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventor: Masaki Okamoto
  • Publication number: 20190348398
    Abstract: There is provided a semiconductor device a method for manufacturing a semiconductor device, and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Applicant: Sony Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Patent number: 10476209
    Abstract: A shield connector includes a first housing and a second housing, a first shield shell configured to cover the first housing, and a second shield shell configured to cover the second housing. The first shield shell includes a first connecting portion and the second shield shell includes a second connecting portion. An electrically conductive fastening member electrically connects the first connecting portion and the second connecting portion to each other. The first housing includes a first fixing portion, and the second housing includes a second fixing portion. The first fixing portion and the second fixing portion are held together by the fastening member in a state in which the first fixing portion and the second fixing portion are interposed between the first connecting portion and the second connecting portion.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 12, 2019
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Masaru Kitagawa, Shinyu Nagashima, Masaki Okamoto, Yasuhiro Kudo
  • Publication number: 20190296494
    Abstract: A shield connector includes a first housing and a second housing, a first shield shell configured to cover the first housing, and a second shield shell configured to cover the second housing. The first shield shell includes a first connecting portion and the second shield shell includes a second connecting portion. An electrically conductive fastening member electrically connects the first connecting portion and the second connecting portion to each other. The first housing includes a first fixing portion, and the second housing includes a second fixing portion. The first fixing portion and the second fixing portion are held together by the fastening member in a state in which the first fixing portion and the second fixing portion are interposed between the first connecting portion and the second connecting portion.
    Type: Application
    Filed: May 12, 2017
    Publication date: September 26, 2019
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Masaru KITAGAWA, Shinyu NAGASHIMA, Masaki OKAMOTO, Yasuhiro KUDO
  • Patent number: 10373934
    Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 6, 2019
    Assignee: Sony Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda