Patents by Inventor Masaki Okuno
Masaki Okuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984216Abstract: A medical image display control device includes a reception unit that receives an input instruction, a creation unit that creates a display image having a tab and a viewer region in which at least a medical image is displayed, the creation unit creating a new display image having a tab and a viewer region different from a viewer region of a display image displayed on a display unit based on the input instruction received by the reception unit, a display controller that performs control such that the tab of the new display image created by the creation unit and the already displayed tab are displayed so as to be selectable on the display unit, and a switching display controller that performs control such that in a case where any tab of the tabs displayed on the display unit is selected, the viewer region corresponding to the selected tab is switched with the already displayed viewer region and is displayed on the display unit.Type: GrantFiled: May 20, 2021Date of Patent: May 14, 2024Assignee: FUJIFILM CorporationInventors: Masaki Miyamoto, Takuma Okuno
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Patent number: 11488913Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: GrantFiled: September 29, 2020Date of Patent: November 1, 2022Assignee: Socionext Inc.Inventors: Akio Hara, Toyoji Sawada, Masaki Okuno, Hirosato Ochimizu
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Publication number: 20210028129Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: ApplicationFiled: September 29, 2020Publication date: January 28, 2021Inventors: Akio HARA, Toyoji SAWADA, Masaki OKUNO, Hirosato OCHIMIZU
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Patent number: 10219813Abstract: A guide pin piercing jig includes a curved frame, a front cylinder unit provided at a front end of the frame, and a rear cylinder unit provided at a rear end of the frame, in which the front cylinder unit has a positioning projection and a boring aiming portion at a tip thereof, the rear cylinder unit has a plurality of parallel guide pin insertion cylinders into which to insert the guide pins and a tentative fixing unit provided at a tip of the rear cylinder unit, and the rear cylinder unit is provided at a rear end of the frame slidably so as be directed to a tip of the front cylinder unit. It becomes possible to aim at a proper portion of a living body bone through which to bore a bone tunnel and to pierce the living body bone with guide pins for hollow drills from behind the living body bone to the proper aiming portion in a proper direction.Type: GrantFiled: November 20, 2014Date of Patent: March 5, 2019Assignees: TEIJIN MEDICAL TECHNOLOGIES CO., LTD., NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITYInventors: Masaki Okuno, Hiroshi Morii, Katsuya Nada, Ryo Kashiwadani, Ryosuke Kuroda
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Patent number: 10004519Abstract: A guide pin piercing jig includes a cylinder unit and a frame having a positioning projection at a tip thereof, in which the cylinder unit has plural parallel guide pin insertion cylinders and tentative fixing unit and is attached to the frame slidably so as to be directed to the tip of the frame. It becomes possible to pierce living body bone with plural guide pins for hollow drills to a proper portion of a living body bone in a proper direction with parallel arrangement to form a bone tunnel that has a rectangular or elliptical opening and is suitable for tendon transplantation.Type: GrantFiled: November 20, 2014Date of Patent: June 26, 2018Assignees: TEIJIN MEDICAL TECHNOLOGIES CO., LTD, NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITYInventors: Masaki Okuno, Hiroshi Morii, Katsuya Nada, Ryosuke Kuroda
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Patent number: 9968368Abstract: A drill guide has a main body in which a drill insertion hole is formed and plural projection portions to be inserted into plural bone tunnels. The plural projection portions project forward from the main body parallel with the center line of the drill insertion hole, a virtual drill insertion hole which extends from the drill insertion hole of the main body is formed between the plural projection portions parallel with their center lines by cutting out confronting portions of the plural projection portions, and the length of at least one of the drill insertion hole and the virtual drill insertion hole is 5 mm or more. The drill guide can guide a drill so as to be correctly between plural bone tunnels bored through a living body bone without causing axis deviation so that a link bone tunnel for connecting the plural bone tunnels can be formed between them in the same direction as their direction.Type: GrantFiled: November 20, 2014Date of Patent: May 15, 2018Assignees: TEIJIN MEDICAL TECHNOLOGIES CO., LTD., NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITYInventors: Masaki Okuno, Hiroshi Morii, Katsuya Nada, Ryosuke Kuroda
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Patent number: 9202759Abstract: A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.Type: GrantFiled: February 27, 2014Date of Patent: December 1, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masaki Okuno, Hajime Yamamoto
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Publication number: 20150182235Abstract: A drill guide has a main body in which a drill insertion hole is formed and plural projection portions to be inserted into plural bone tunnels. The plural projection portions project forward from the main body parallel with the center line of the drill insertion hole, a virtual drill insertion hole which extends from the drill insertion hole of the main body is formed between the plural projection portions parallel with their center lines by cutting out confronting portions of the plural projection portions, and the length of at least one of the drill insertion hole and the virtual drill insertion hole is 5 mm or more. The drill guide can guide a drill so as to be correctly between plural bone tunnels bored through a living body bone without causing axis deviation so that a link bone tunnel for connecting the plural bone tunnels can be formed between them in the same direction as their direction.Type: ApplicationFiled: November 20, 2014Publication date: July 2, 2015Inventors: Masaki OKUNO, Hiroshi MORII, Katsuya NADA, Ryosuke KURODA
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Publication number: 20150150570Abstract: A guide pin piercing jig includes a curved frame, a front cylinder unit provided at a front end of the frame, and a rear cylinder unit provided at a rear end of the frame, in which the front cylinder unit has a positioning projection and a boring aiming portion at a tip thereof, the rear cylinder unit has a plurality of parallel guide pin insertion cylinders into which to insert the guide pins and a tentative fixing unit provided at a tip of the rear cylinder unit, and the rear cylinder unit is provided at a rear end of the frame slidably so as be directed to a tip of the front cylinder unit. It becomes possible to aim at a proper portion of a living body bone through which to bore a bone tunnel and to pierce the living body bone with guide pins for hollow drills from behind the living body bone to the proper aiming portion in a proper direction.Type: ApplicationFiled: November 20, 2014Publication date: June 4, 2015Inventors: Masaki OKUNO, Hiroshi MORII, Katsuya NADA, Ryo KASHIWADANI, Ryosuke KURODA
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Publication number: 20150150567Abstract: A guide pin piercing jig includes a cylinder unit and a frame having a positioning projection at a tip thereof, in which the cylinder unit has plural parallel guide pin insertion cylinders and tentative fixing unit and is attached to the frame slidably so as to be directed to the tip of the frame. It becomes possible to pierce living body bone with plural guide pins for hollow drills to a proper portion of a living body bone in a proper direction with parallel arrangement to form a bone tunnel that has a rectangular or elliptical opening and is suitable for tendon transplantation.Type: ApplicationFiled: November 20, 2014Publication date: June 4, 2015Inventors: Masaki OKUNO, Hiroshi MORII, Katsuya NADA, Ryosuke KURODA
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Publication number: 20140179081Abstract: A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.Type: ApplicationFiled: February 27, 2014Publication date: June 26, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masaki OKUNO, Hajime YAMAMOTO
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Patent number: 8697526Abstract: A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.Type: GrantFiled: November 21, 2011Date of Patent: April 15, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Masaki Okuno, Hajime Yamamoto
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Patent number: 8692331Abstract: A semiconductor device includes a gate electrode formed over a semiconductor substrate, and a sidewall spacer formed on a sidewall of the gate electrode. The sidewall spacer formed along the sidewall parallel to a gate length direction of the gate electrode has a first thickness, and the sidewall spacer formed along the sidewall parallel to a gate width direction of the gate electrode has a second thickness that is greater than the first thickness.Type: GrantFiled: July 3, 2013Date of Patent: April 8, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Masaki Okuno
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Publication number: 20130292779Abstract: A semiconductor device includes a first p-channel FET, the first p-channel FET includes: a first fin-type semiconductor region; a first gate electrode crossing the first fin-type semiconductor region and defining a first p-channel region at an intersection of the first fin-type semiconductor region and the first gate electrode; p-type first source/drain regions, each formed on either side of the first gate electrode in the first fin-type semiconductor region; and first and second compressive stress generating regions formed by oxidizing regions located outside the p-type first source/drain regions in the first fin-type semiconductor region.Type: ApplicationFiled: March 29, 2013Publication date: November 7, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Masaki Okuno
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Publication number: 20130292749Abstract: A semiconductor device includes a gate electrode formed over a semiconductor substrate, and a sidewall spacer formed on a sidewall of the gate electrode. The sidewall spacer formed along the sidewall parallel to a gate length direction of the gate electrode has a first thickness, and the sidewall spacer formed along the sidewall parallel to a gate width direction of the gate electrode has a second thickness that is greater than the first thickness.Type: ApplicationFiled: July 3, 2013Publication date: November 7, 2013Inventor: Masaki Okuno
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Patent number: 8507990Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.Type: GrantFiled: November 2, 2011Date of Patent: August 13, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Masaki Okuno
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Publication number: 20120220094Abstract: A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.Type: ApplicationFiled: November 21, 2011Publication date: August 30, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masaki OKUNO, Hajime YAMAMOTO
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Publication number: 20120043613Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.Type: ApplicationFiled: November 2, 2011Publication date: February 23, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Masaki Okuno
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Patent number: 8071448Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.Type: GrantFiled: August 19, 2009Date of Patent: December 6, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Masaki Okuno
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Publication number: 20090309141Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.Type: ApplicationFiled: August 19, 2009Publication date: December 17, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Masaki Okuno