Abstract: A liquid crystal display device (1) according to one embodiment of the present invention includes a timing controller (4) which, (i) in a first display mode, in which a number of tones that each pixel is capable of displaying is smaller than a predetermined number, controls a scanning signal and a data signal by an interlace driving method, by which a single frame includes a plurality of fields, and (ii) in a second display mode, in which the number of tones that each pixel is capable of displaying is equal to or greater than the predetermined number, controls the scanning signal and the data signal by a progressive driving method.

Abstract: An auxiliary wire, which can be connected to each of a plurality of data signal lines (Sn), is constituted by (i) a first auxiliary wire (17) provided so as to intersect the plurality of data signal lines (Sn) on a side where end parts of the respective plurality of data signal lines (Sn) are connected to a data signal line driving circuit (4) and (ii) a second auxiliary wire (18) provided so as to intersect the plurality of data signal lines (Sn) on a side of the other end parts of the respective plurality of data signal lines (Sn). Between the first auxiliary wire (17) and the second auxiliary wire (17), there are provided (i) a positive-polarity amplifier circuit (6) for receiving a positive data signal from the data signal line driving circuit (4) and (ii) a negative-polarity amplifier circuit (7) for receiving a negative data signal from the data signal line driving circuit (4).

Abstract: In a display device that can use a low frequency drive method, in the case of low frequency drive, in a data correction unit (23) of a display control circuit (200), a pixel grayscale value is set such that the differential value between the potential difference between the pixel electrode and the common electrode when a voltage of positive polarity is applied and the potential difference between the pixel electrode and the common electrode when a voltage of negative polarity is applied becomes larger than during normal drive. With this, a correction amount (shift amount) is made larger during low frequency drive than during normal drive, whereby flickers and ghosting during low frequency drive are prevented.

Abstract: A gate driver (24) which is provided by an IGZO-GDM and a level shifter circuit (13) are connected to each other via a first through a fifth wires (OL1 through OL5). Each wire (OL) is connected to a discharge unit (190). If an electric power supply to a first through a fifth output circuits (OC1 through OC5) in the level shifter circuit (13) becomes lower than a lower operation limit value during a power-off sequence which is supposed to remove a residual charge from inside a panel, outputs from the first through the fifth output circuits (OC1 through OC5) assume a high-impedance state, whereupon a potential on each wire (OL) is drawn by a discharge unit (190) into a ground potential. Therefore, residual charge inside the panel is removed quickly and stably when power supply is shut off.

Abstract: The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.

Abstract: In order to provide a display device and a method for driving a display device, each of which is capable of repairing a disconnection in a data signal line and further reduces electric power consumption, a display device (1) includes a repair amplifier control section (14) for causing a repair amplifier circuit (12) to operate at a low-performance level during any period within a period from when scanning of pixels in the display area in the display device (1) is finished to when next scanning is started.

Abstract: The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.

Abstract: A liquid crystal display device includes a gate driver, a source driver and a common driver. An input video signal is stored in a line memory and a gray scale with which an applied voltage becomes highest is detected from data corresponding to 1 line among the signal. A common electrode is driven by a common voltage being reduced in accordance with the gray scale and having a low effective value. The driver is driven by an output controlled in accordance with the voltage thus reduced. A voltage applied to a common electrode is set by using a LUT and a common voltage is set by using a LUT. It is therefore possible to provide a liquid crystal display device and a method of driving the liquid crystal display device, each of which can reduce power consumption.

Abstract: The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.

Abstract: The present invention is intended to make it unlikely that, in a case where a transistor is turned on in preparation for an operation to turn off a power source of a liquid crystal display device, a DC voltage becomes applied across a pixel even if potential variation (kickback) occurs at a pixel electrode in reaction to a change in status of the transistor from an on state to an off state.

Abstract: A liquid crystal display device includes: a data signal line; a scan signal line; a pixel electrode; a transistor connected to (i) the data signal line, (ii) the scan signal line, and (iii) the pixel electrode; and a common electrode, the liquid crystal display device being configured to turn on the transistor during a power-off sequence by causing a change in an electric potential of the scan signal line, the electric potential of the scan signal line reaching a first electric potential at a first timing after the change is initiated, and the common electrode being in an electrically floating state at a second timing which comes after the first timing.

Abstract: The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.

Abstract: A liquid crystal driving circuit is disclosed which carries out time-division driving with respect to each pixel constituting a liquid crystal display panel by causing a bright and dark frame period and a positive and negative frame period to be different from each other, the bright and dark frame period being a period of brightness and darkness of luminance at which to drive the each pixel, the positive and negative frame period being a period of polarities of a voltage to be applied to liquid crystal of the each pixel.

Abstract: The objective of the present invention is to suppress the occurrence of flickering and to reduce the power consumption of a display device. A liquid crystal display device that is an embodiment of the present invention splits one frame into a plurality of fields and performs interlaced driving, and has a timing controller that, with a predetermined number of selected pixels in the direction of a scanning line and a signal line as units, is for reversing the polarity of a data signal applied to selected pixels in a field in a manner so that there is the same number of positive and negative polarities of the data signal applied to the selected pixels disposed along a signal line, and is for reversing the polarity in a manner such that the polarity of the data signal applied to the selected pixels changes for each frame.

Abstract: The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.

Abstract: A display module of the present invention includes first through third source drivers (6-1 through 6-3) (i) which are provided for respective regions into which a display region is divided and (ii) each of which includes an analysis circuit and receives a video signal for a corresponding one of the regions but receives no video signal for the regions other than the corresponding one of the regions. The third source driver (6-3) supplies, to the first and second source drivers (6-1 and 6-2), gamma (?) setting information (19) for generating a source signal to be outputted from each of the first and second source drivers (6-1 and 6-2). The first and second source drivers (6-1 and 6-2) output respective analysis results (5a and 5b) from the respective analysis circuits. The third source driver (6-3) outputs a PWM signal (14) for controlling the light irradiation section.

Abstract: A source AMP output circuit (10) is provided with a switching circuit (17) for carrying out the following operation. That is, in a case where a polarity is reversed, the switching circuit (17) disconnects a data signal line (S(M)) from output terminals of a positive amplifier circuit (15) and a negative polarity amplifier circuit (16) each included in the source AMP output circuit (10), and then connects the data signal line S(M) to a power supply which is in a power supply voltage range (Vdd1 to Vdd3) of the positive polarity amplifier circuit (15) or to a power supply which is in a power supply voltage range (Vdd2 to Vdd4) of the negative polarity amplifier circuit (16).

Abstract: In order to provide a display device and a method for driving a display device, each of which is capable of repairing a disconnection in a data signal line and further reduces electric power consumption, a display device (1) includes a repair amplifier control section (14) for causing a repair amplifier circuit (12) to operate at a low-performance level during any period within a period from when scanning of pixels in the display area in the display device (1) is finished to when next scanning is started.

Abstract: Provided for each data signal line drive circuit (6a, 6b, 6c) are: a voltage generation circuit (61a, 61b, 61c) that generates a drive voltage in accordance with an external voltage; and a voltage determination circuit (63a, 63b, 63c) which determines whether or not a voltage level of at least either the external voltage or the drive voltage falls within a range of allowable voltages, in a case where the voltage level does not fall within the range of allowable voltages, operation of the voltage generation circuits (61a, 61b, 61c) being stopped.

Abstract: A display device (10) includes a timing control section (13) and a signal line drive circuit (16), either of which receives a lower power supply voltage level than the other, and a level changing circuit (20) for changing an amplitude level (T) of a reset signal (B). The timing control section (13) and the level changing circuit (20) receive the reset signal (B). The level changing circuit (20) changes the amplitude level (T) of the supplied reset signal (B) and then supply, to the signal line drive circuit (16), a reset signal (Ba) with a converted amplitude level. This makes it possible to achieve an image display with low power consumption and a stable display quality.