Abstract: In a microcomputer, a programmable memory such as a flash EEPROM has a first memory region and a second memory region. In this case, the first memory region stores an application program, while the second memory region storing a boot program for rewriting the application program. Under this condition, a selecting circuit selects the first memory region except the second memory region. Further, only the selected first memory region is erased.

Abstract: It is intended to provide a microcomputer which does not require to have a programmable RAM therein, or to have an external memory, and can attain erase/write of a program. The microcomputer comprises an EEPROM 2, a ROM 3 storing a program indicating an erase and write procedure of the EEPROM (hereinafter called a boot program), and a CPU 5, wherein there is provided a mode to select a boot program in the EEPROM and a program in the ROM by an address to be accessed, and to executed the selected one with the CPU.

Abstract: An INTC and a CPU are interconnected via a bus. A first line through which an interrupt request signal is transferred to the CPU from the INTC, and a second line through which an interrupt reception signal is transferred from the CPU to the INTC. The INTC outputs both of a vector address and an interrupt mode signal to a bus in response to the interrupt reception signal. The CPU receives the vector address and the interrupt mode signal and carries out the interrupt processing on the basis of these signals. In this way, since the INTC outputs both the vector address and the interrupt processing mode signal by using the bus, it is possible to reduce a number of terminals for connecting the CPU and the INTC with each other.

Abstract: The present invention is an information processing device enabling to surely carry out interrupt processing by outputting an interrupt signal even if a breakpoint is set in or after the second byte of an instruction code. The information processing device of the present invention is configured such that when having received the break signal that is output at the time of detection of a breakpoint set in or after the second byte of the instruction code, the information processing device stores the event of input of the break signal, outputs the interrupt signal at the timing of completion of execution of the instruction code and generates an interrupt.