Patents by Inventor Masako Murofushi

Masako Murofushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070075282
    Abstract: A radiation image storage panel comprises a layer containing an europium activated cesium bromide stimulable phosphor. The europium activated cesium bromide stimulable phosphor has a structure such that a ratio of a signal intensity, which corresponds to g=1.90 with respect to europium activated cesium bromide and which is taken in an ESR spectrum at a Q-band, to the signal intensity, which corresponds to g=1.88 with respect to europium activated cesium bromide and which is taken in the ESR spectrum at the Q-band, is equal to at least 0.7. The radiation image storage panel is produced with a process, wherein a vapor phase deposited film, which contains pillar-shaped crystals of the europium activated cesium bromide stimulable phosphor, is formed on the base plate in a vacuum atmosphere and is then subjected to heat processing in the vacuum atmosphere.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 5, 2007
    Inventors: Takashi Komiyama, Masako Murofushi, Kenji Takahashi
  • Patent number: 6110222
    Abstract: A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: August 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Minami, Masako Murofushi
  • Patent number: 5913101
    Abstract: In order to modify a combination of logic gates based on relationships between physical locations of the logic gates in a semiconductor integrated circuit which has already been subjected to layout design in the middle of design of the semiconductor integrated circuit, circuit portions whose combination is to be modified are specified, then the circuit portions are transformed into logically equivalent intermediate representations (NAND2s, IVs, etc.), then anew combination of the logic gates is generated based on the intermediate representation, and then the prior combination of the logic gates is replaced with the new combination of the logic gates.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: June 15, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Murofushi, Takashi Ishioka
  • Patent number: 5191542
    Abstract: Disclosed is an automatic floorplan operation apparatus for automatically performing a layout of cells onto a plurality of arrangeable areas which are optionally permitted to be overlapped on a chip. This apparatus evaluates degrees of cell densities in the respective arrangeable areas based on cell distributions therein by an objective function. When the evaluation is insufficient, an area definition correction unit also provided in the apparatus corrects the cell densities in accordance with FDM so that the cell densities in the overlapped and the independent areas are made uniform. This correction is carried out by a shift routine and a transformation routine, and is automatically repeated until the most suitable floorplan can be obtained.
    Type: Grant
    Filed: May 15, 1990
    Date of Patent: March 2, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masako Murofushi