Abstract: A method and circuit for accurately detecting an output short circuit in a switching regulator. A first transistor and a second transistor are connected in series and driven in a complementary manner. A comparator compares output current, which is generated when the first and second transistors are driven, with a short circuit detection threshold to generate a first short circuit detection signal. A timing controller retrieves the first short circuit detection signal generated by the comparator at a predetermined time to generate a second short circuit detection signal.

Abstract: A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

Abstract: A regulator circuit for reducing the output noise when regulators are switched includes a linear regulator and a switching regulator. The linear regulator generates a first regulator voltage from an input voltage with a first feedback loop. The switching regulator generates a second regulator voltage from the input voltage with a second feedback loop, which is connected to the first feedback loop. A loop control circuit controls the first feedback loop so as to lower the first regulator voltage when the switching regulator is activated.

Abstract: A regulator circuit for reducing the output noise when regulators are switched includes a linear regulator and a switching regulator. The linear regulator generates a first regulator voltage from an input voltage with a first feedback loop. The switching regulator generates a second regulator voltage from the input voltage with a second feedback loop, which is connected to the first feedback loop. A loop control circuit controls the first feedback loop so as to lower the first regulator voltage when the switching regulator is activated.

Abstract: A power supply circuit that accurately generates output voltages with the same regulator includes a regulator for generating a first output voltage from an input voltage. A first switch circuit, connected to the regulator, selectively outputs the first output voltage of the regulator as a second output voltage from the power supply circuit. A pre-charge circuit, connected to the regulator and the first switch circuit, generates the second output voltage from the input voltage before the first output voltage of the regulator is output as the second output voltage while controlling the first switch circuit.

Abstract: A method for selecting cells in response to input codes of a digital-to-analog converter distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C01 through C63. A prime number of, or 61, current source cells are used as cyclically selected cells. That is, 61 current source cells C02-C62, ranging from the second left-most current source cell C02 to the second right-most current source cell C62, are used as cyclically selected cells. The remaining left-most current source cell C01 and right-most current source cell C63 are used as non-cyclically selected cells. The cyclically selected cells, including the 61 current source cells, are selected in response to input codes using a Data Weighted Average (DWA) technique.

Abstract: It is an objective to provide a digital-to-analog converter circuit that allows the value of the current output from each current source cell to be identical, regardless of the position of that current source cell relative to the power supply line. To ensure that the voltages supplied to the respective current source cells are identical, the power supply lines La and Lb are disposed in the form of a right triangle modified such that their line widths W1 and W2 become constantly narrower on one side depending on the position at which the power supply lines La and Lb are formed. The power supply lines La and Lb are also disposed such that their hypotenuses are opposite to each other.

Abstract: It is an objective to provide a method for selecting cells in response to input codes of a digital-to-analog converter, which distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C01 through C63. A prime number of, or 61, current source cells are used as cyclically selected cells, that is, 61 current source cells C02-C62, ranging from the second left-most current source cell C02 to the second right-most current source cell C62, are used as cyclically selected cells. The remaining left-most current source cell C01 and right-most current source cell C63 are used as non-cyclically selected cells. The cyclically selected cells comprised of 61 current source cells are selected in response to input codes according to the DWA technique.

Abstract: It is an objective to provide a digital-to-analog converter circuit that allows the value of the current output from each current source cell to be identical, regardless of the position of that current source cell relative to the power supply line. To ensure that the voltages supplied to the respective current source cells are identical, the power supply lines La and Lb are disposed in the form of a right triangle modified such that their line widths W1 and W2 become constantly narrower on one side depending on the position at which the power supply lines La and Lb are formed. The power supply lines La and Lb are also disposed such that their hypotenuses are opposite to each other.

Abstract: A digital-to-analog conversion circuit including a plurality of unit current output cells (1) arranged in a matrix. Each of the current output cells (1) includes a unit current source (11) having a power supply input and a current output, and a selecting switch (12) connected to the current output and having two switching output terminals. The circuit further includes at least one ½ and/or ¼ weighted current output cell (2) disposed on a row in the matrix, and at least one ½ and/or ¼ supplementary current source (8) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.

Abstract: An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.

Abstract: The A/D converter comprises a resistor series (30), a plurality of first comparators (1) and a plurality of second comparators (2). Resistor series (30) has a plurality of resistors(R) connected in series between two terminals to which predetermined reference voltages are applied. First comparator (1) compares a node voltage between resistors and an analog voltage signal to be compared. Second comparator (2) compares an average voltage of the two node voltages across each resistor R and the analog voltage signal. First and second comparators (1,2) are disposed alternatively.

Abstract: A vertical contour correcting circuit that provides contour correction of a luminance signal at a horizontal color transition area of an image, thereby minimizing dot interference at the color transition area of a reproduced image. The vertical contour correcting circuit includes a vertical band-pass filter which outputs a level difference signal. The level difference signal is delayed to produce a first delay signal. The first delay signal is delayed to produce a second delay signal. An intermediate value signal is determined from the level difference signal, the first delay signal, and the second delay signal. The intermediate value signal and the first delay signal are added together so that their carrier color signal band components are canceled out.

Abstract: A circuit that separates a luminance signal and a color signal so that dot interference in a color transition area of a reproduced image is minimized. A color video signal is transmitted to an adaptive bandpass filter via a vertical carrier color signal extraction filter. An output signal from the adaptive bandpass filter represents the color signal portion of the color video signal. The color signal is subtracted from the color video signal via a subtractor circuit to produce the luminance signal portion of the color video signal. Since the output signal of the bandpass filter is subtracted from the color video signal, the luminance signal portion of the color video signal is separated without being affected by different colors before and after a color transition point.