Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.

Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.

Abstract: A receiver receives frequency division multiplexing transmission signals of multiple carriers, and includes a difference detection unit, an integration unit, a noise detection unit, a selection unit, and a correction unit. The difference detection unit calculates a difference that is representative of the amount of noise in the frequency division multiplexing transmission signals. The integration unit integrates for each frequency of the multiple carriers the difference output of the difference detection unit. The noise detection unit determines whether or not impulse noise is present in the input signal. When impulse noise is present, the selection unit supplies the integrator output to the correction unit. When impulse noise is not present, the selection unit supplies the calculated difference output to the correction unit.

Abstract: A frequency domain-equalizing device receives a digitally modulated single-carrier signal and carries out multipath equalization in a frequency domain. This frequency domain-equalizing device includes a frequency domain-conversion module, a transmission path response-estimation module, an equalization module, an interference decision module, a correction module, and a time-domain conversion module. The interference decision module determines whether at least some portion of a signal is interference and the correction module corrects the signal according to the determination of the interference decision module.

Abstract: According to one embodiment, an error correcting decoder includes a first error correction decoding module, an interleaving module, a delay module, a second error correction decoding module, and a corrector. The first error correction decoding module performs a first error correction decoding to a received signal in accordance with a broadcasting system. The interleaving module rearranges a data array of an output of the first error correction decoding module in a second order. The data array is ordered in a first order which is reverse to the second order. The delay module delays the received signal by a processing time of the first error correction decoding module. The second error correction decoding module performs a second error correction decoding to an output of the interleaving module and an output of the delay module. The corrector configured to correct a delay of an output of the second error correction decoding module based on a packet position defined by the broadcasting system.

Abstract: A receiver receives frequency division multiplexing transmission signals of multiple carriers, and includes a difference detection unit, an integration unit, a noise detection unit, a selection unit, and a correction unit. The difference detection unit calculates a difference that is representative of the amount of noise in the frequency division multiplexing transmission signals. The integration unit integrates for each frequency of the multiple carriers the difference output of the difference detection unit. The noise detection unit determines whether or not impulse noise is present in the input signal. When impulse noise is present, the selection unit supplies the integrator output to the correction unit. When impulse noise is not present, the selection unit supplies the calculated difference output to the correction unit.

Abstract: A receiving apparatus includes a demodulation means for demodulating a transmission signal to output a demodulation output having a predetermined number of bits; a reliability calculation means for calculating reliability of the transmission signal to output reliability information; a conversion processing means for reducing the number of bits of the demodulation output on the basis of the reliability information, and for multiplexing the demodulation output having the reduced number of bits and the reliability information to output the multiplexed result; and a deinterleave means for deinterleaving the output of the conversion processing means.

Abstract: According to one embodiment, an error correcting decoder includes a first error correction decoding module, an interleaving module, a delay module, a second error correction decoding module, and a corrector. The first error correction decoding module performs a first error correction decoding to a received signal in accordance with a broadcasting system. The interleaving module rearranges a data array of an output of the first error correction decoding module in a second order. The data array is ordered in a first order which is reverse to the second order. The delay module delays the received signal by a processing time of the first error correction decoding module. The second error correction decoding module performs a second error correction decoding to an output of the interleaving module and an output of the delay module. The corrector configured to correct a delay of an output of the second error correction decoding module based on a packet position defined by the broadcasting system.

Abstract: A frequency division multiplex transmission signal receiving apparatus for receiving a frequency division multiplex transmission signal using a plurality of carries includes: an estimation section estimating a transfer function of a received signal after the received signal has been transformed into a frequency domain signal; a demodulation section demodulating the received signal according to the transfer function estimated by the estimation section; a plurality of variation detecting sections performing variation detection using a plurality of different variation detection methods, based on the transfer function estimated by the estimation section; a reliability determining section determining reliability based on a result of a combination of variation detection results of the plurality of variation detecting sections; and a correction section performing error correction of the demodulated signal from the demodulation section, the demodulated signal being subjected to an application of a reliability determi

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.

Abstract: An equalization apparatus configured to receive a digitally modulated single carrier signal and perform multipath equalization in a frequency domain, including a frequency domain conversion unit which converts a received signal to a frequency domain signal, a channel estimation unit configured to estimate a channel response in a frequency domain from the received signal, an equalization weight calculation unit which calculates an equalization weight from the channel estimate value in the frequency domain, an equalization filter which receives the frequency domain signal from the frequency domain conversion unit and the equalization weight from the equalization weight calculation unit and performs equalization processing and a time domain conversion unit which converts the frequency domain signal from the equalization filter to a time domain signal, wherein the equalization weight calculation unit includes a power calculation unit, a power value correction unit, a complex conjugate generator and a divider.

Abstract: According to an embodiment, a channel estimator includes a channel response estimation section configured to estimate a channel response by correlation processing between a received signal and a known pattern signal; a path power calculation section configured to measure power of each path within an output of the channel response estimation section; a noise power calculation section configured to measure noise power from the output of the channel response estimation section; a path determination section configured to determine paths to be preserved by using the path power outputted from the path power calculation section and the noise power outputted from the noise power calculation section; and a noise removal section configured to remove values in time domain excepting the paths determined at the path determination section, from the output of the channel response estimation section.

Abstract: A channel estimator includes: a delay time estimation section configured to estimate a delay time of a received signal; an FFT parameter determination section configured to determine an FFT window position and an FFT size according to the estimated delay time; a first and a second FFT sections configured to transform the received signal and a known pattern signal, respectively, to the frequency domain based on the FFT window position and the FFT size that are determined; a channel response calculation section configured to perform division processing to divide the output of the first FFT section by the output of the second FFT section; and an IFFT section configured to apply IFFT to the output of the channel response calculation section based on the determined FFT size, and the delay time estimation section estimates a delay time based on the output of the IFFT section.

Abstract: A receiver includes a receiving section configured to receive digital broadcasts; a demodulating section configured to demodulate a signal received by the receiving section and output a frame-based signal including a plurality of symbols; a detecting section configured to detect a symbol position in a frame-based signal provided from the demodulating section; a decoding section configured to decode a frame-based signal from the demodulating section in accordance with a symbol position; a symbol counter configured to output a count output specifying a symbol position in a signal decoded in the decoding section; and a control section configured to control counting of the symbol counter on the basis of a symbol position detected by the detecting section and on a count value of the symbol counter.

Abstract: A receiver has a plurality of synthesizers configured to synthesize signals received by N pieces of antennas by using weighted coefficients different from each other, where N is an integer of two or more, a determination part configured to determine an output signal having a minimum error among output signals of the plurality of synthesizers in units of a predetermined transmission unit, and a re-synthesis part configured to sequentially re-synthesize and output a signal determined to have the minimum error by the determination part.

Abstract: A frame number detecting device includes: a symbol counter that receives a received signal including frames each of which is formed of a predetermined number of symbols, and outputs a count value as a symbol number for each of the symbols by incrementing the count value by one every time one symbol is inputted, each of the frames including a frame synchronization signal including a part obtained by shifting a frame synchronization signal of a different frame on a symbol-by-symbol basis according to a predetermined rule; a sequence storage that stores a synchronization sequence based on at least one of the frame synchronization signals included in the received signal, and a pattern matching unit that performs pattern matching between the synchronization sequence stored in the sequence storage and the received signal.

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.

Abstract: A frequency division multiplex transmission signal receiving apparatus for receiving a frequency division multiplex transmission signal using a plurality of carries includes: an estimation section estimating a transfer function of a received signal after the received signal has been transformed into a frequency domain signal; a demodulation section demodulating the received signal according to the transfer function estimated by the estimation section; a plurality of variation detecting sections performing variation detection using a plurality of different variation detection methods, based on the transfer function estimated by the estimation section; a reliability determining section determining reliability based on a result of a combination of variation detection results of the plurality of variation detecting sections; and a correction section performing error correction of the demodulated signal from the demodulation section, the demodulated signal being subjected to an application of a reliability determi

Abstract: A receiving apparatus includes a demodulation means for demodulating a transmission signal to output a demodulation output having a predetermined number of bits; a reliability calculation means for calculating reliability of the transmission signal to output reliability information; a conversion processing means for reducing the number of bits of the demodulation output on the basis of the reliability information, and for multiplexing the demodulation output having the reduced number of bits and the reliability information to output the multiplexed result; and a deinterleave means for deinterleaving the output of the conversion processing means.

Abstract: A receiver includes a receiving section configured to receive digital broadcasts; a demodulating section configured to demodulate a signal received by the receiving section and output a frame-based signal including a plurality of symbols; a detecting section configured to detect a symbol position in a frame-based signal provided from the demodulating section; a decoding section configured to decode a frame-based signal from the demodulating section in accordance with a symbol position; a symbol counter configured to output a count output specifying a symbol position in a signal decoded in the decoding section; and a control section configured to control counting of the symbol counter on the basis of a symbol position detected by the detecting section and on a count value of the symbol counter.