Abstract: Blocks in two different frames are subjected to Hadamard transform by first and second Hadamard transform circuits, and a sum component and a difference component are calculated for the components of the two blocks corresponding to each other to perform three-dimensional Hadamard transform, so that detection is made as to whether or not these blocks include a motion. While the sum component and the difference component are encoded for the block determined as including a motion, a motion detection result, rather than the difference component, is encoded for the block determined as including no motion. As a result, a high compression ratio can be achieved in video encoding with a small-scale circuit.

Abstract: It is possible to control the number of generated codes while retraining deterioration of an image quality by an encoding circuit constituted so as to select any of a first image signal not decreasing information quantity and a second image signal decreasing information quantity in accordance with the accumulated value of the number of codes.

Abstract: Provided is a video signal processing circuit capable, in a scale conversion, of rendering a circuit scale small and alleviating a deterioration of a vertical resolution. A vertical scaler is provided with a function of increasing the number of scanning lines of an input video signal. An increasing rate thereof is adjacent to 1.0. In a case that the number of unit output lines is M, the number of unit input lines is N, and the increasing rate is ?, a condition of 0<?<2 is satisfied. That is, ? is adjacent to 1.0. A number-of-a-plurality-of-time reading-out circuit performs a reading-out by a 3-time clock toward the input video signal. In addition, the number-of-a-plurality-of-time reading-out circuit is configured in such a manner as not to select the video signal read out by an address overtaking. A horizontal scaler interpolates the number of dots of a horizontal direction according to the number of horizontal dots of a liquid crystal panel.

Abstract: A liquid crystal panel receives a ?2 as an operation clock, and receives a digital video signal (D or E) from a selection circuit. The digital video signal (D or E) is output in a period half a ?2 period. The operation clock of the panel is the ?2. Thus, the same dot data (a same-location signal value in the video signal) in the video signal is successively supplied to adjacent two dots aligned horizontally on the liquid crystal panel. At timing of a first field, an input digital video signal (B) is not delayed, and is supplied to the liquid crystal panel 20 as the digital video signal (D). At timing of a second field, the input digital signal B is delayed, and supplied to the liquid crystal panel as a 1-clock-delay video signal (E).

Abstract: It is possible to control the number of generated codes while retraining deterioration of an image quality by an encoding circuit constituted so as to select any of a first image signal not decreasing information quantity and a second image signal decreasing information quantity in accordance with the accumulated value of the number of codes.

Abstract: Blocks in two different frames are subjected to Hadamard transform by first and second Hadamard transform circuits, and a sum component and a difference component are calculated for the components of the two blocks corresponding to each other to perform three-dimensional Hadamard transform, so that detection is made as to whether or not these blocks include a motion. While the sum component and the difference component are encoded for the block determined as including a motion, a motion detection result, rather than the difference component, is encoded for the block determined as including no motion. As a result, a high compression ratio can be achieved in video encoding with a small-scale circuit.

Abstract: Provided is a video signal processing circuit capable, in a scale conversion, of rendering a circuit scale small and alleviating a deterioration of a vertical resolution. A vertical scaler is provided with a function of increasing the number of scanning lines of an input video signal. An increasing rate thereof is adjacent to 1.0. In a case that the number of unit output lines is M, the number of unit input lines is N, and the increasing rate is ?, a condition of 0<?<2 is satisfied. That is, ? is adjacent to 1.0. A number-of-a-plurality-of-time reading-out circuit performs a reading-out by a 3-time clock toward the input video signal. In addition, the number-of-a-plurality-of-time reading-out circuit is configured in such a manner as not to select the video signal read out by an address overtaking. A horizontal scaler interpolates the number of dots of a horizontal direction according to the number of horizontal dots of a liquid crystal panel.

Abstract: A video signal reproducing apparatus, such as a video disc player, equipped with a field memory for special reproduction such as still-picture reproduction. The video signal writing-reading period for the field memory is set to a value which is the color subcarrier period multiplied by an integer, is also the horizontal synchronizing period multiplied by an integer and is further approximate to one field period to the greatest possible extent, to thereby eliminate the discontinuity of video signals due to the track jumping action of the pickup.

Abstract: In normal reproduction, a switch circuit (11) is set to select an output signal of an A/D converter (1). Consequently, a movement adaptation type YC separating circuit is formed, whereby a luminance signal and a chrominance signal are separated. When a control signal is outputted from a control signal generating circuit (12) in response to an instruction of still picture reproduction, the switch circuit (11) selects an output signal of the last output terminal of delay means formed by line memory (2) or frame memory (3) and inputs the selected signal to the first input terminal of the delay means. As a result, in still picture reproduction, a circulating circuit where the inputted composite video signal circulates in the delay means is formed and a luminance signal and a chrominance signal are separated based on a plurality of composite video signals having different delay times obtained from the circulating circuit.

Abstract: A scanning conversion method prepares, in order to convert 2:1 interlace scanning video signals formed by (2N+1)/2 lines (N: positive integer) into progressive scanning system video signals, a memory (23) having addresses corresponding to N+1 lines. The address of the memory (23) for N+1 lines are circulated thereby to progressively write the interlace scanning video signals in the addresses while reading the signals from the addresses subjected to the writing at a speed twice that in the writing repeatedly twice.