Abstract: A current programming apparatus having two data lines for a pixel line is presented. An image data current is supplied to the first and the second data lines alternatively by switching M1 and M2 complementally. By switching M7 and M8 on during the switches M1 and M2 turn on respectively, a constant current is supplied to the data line to which the data current is not supplied. The scanning signals are applied so as to write a constant current into pixels immediately before the data current is written. Thus a write-in defect by a fluctuation in the threshold voltages is prevented.

Abstract: Even if characteristics of transistors differ every circuit, in order to suppress an influence by the different characteristics and stabilize the programming operation to a control electrode of a drive transistor even if a data signal is small, there is provided a programming apparatus for programming signals which are supplied to a circuit array (61, 62) having a plurality of circuits each having transistors (M11, M12), first switching elements (M21, M22) connected to control electrodes of the transistors, and second switching elements (M31, M32) each connected to one main electrode of each of the transistors.

Abstract: A current programming apparatus includes a current source; a plurality of first circuits to which data currents are supplied through a data line, the first circuits commonly connected with the data line; a second circuit having a terminal connected to the current source; a switch connecting or breaking the second circuit with or from the data line, wherein the current source generates a predetermined current to supply the generated current to the second circuit through the terminal while the switch is off, whereby the value of the predetermined current is written in the second circuit, and wherein the current source generates a current based on data, and the second circuit generates a current based on the written value of the predetermined current, and a difference current between the current generated by the current source and the current generated by second circuit is supplied to the first circuits through the data line while the switch is on, whereby the value of the current is written in the first circuit

Abstract: An active matrix type display apparatus in which a plurality of pixel circuits each having an electroluminescent element EL, a 1st FET to control a current flowing in the EL, and a 2nd FET provided between a gate and a drain of the 1st FET are arranged in a matrix, the plurality of pixel circuits arranged in one direction are connected to a data line every column, the 2nd FET is turned on for a predetermined time period, and an image data current flowing in the data line is supplied to the gate and drain of the 1st FET, thereby writing a current value of the image data current. A preliminary charging circuit is connected to the data line. Before the writing operation in the predetermined time period is expired, a current of a predetermined current value is applied to the image data current so that a gate-source voltage of the 1st FET is equal to or larger than a threshold value. Thus, writing imperfection due to a variation in threshold voltage of the 1st FET is solved.

Abstract: A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied.

Abstract: A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.

Abstract: A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.

Abstract: A pixel modulation apparatus for converting pixel data D composed of N1 bits to a pixel data signal composed of one bit. The pixel data D is input into the apparatus at a pixel period T0. The apparatus includes a first data conversion unit which converts the pixel data D to pixel data D1 expanded to N2 bits (N2>N1) at the period T0, a second data conversion unit which converts the pixel data D1 to pixel data D2 composed of N3/m bits at a period T0/m, a third data conversion unit which inputs n data from among the pixel data D2 and pixel data Dd2 constituting the pixel data D2 before having the period T0/m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the n data to pixel data D3 composed of N3 bits, including additional data corresponding to the predetermined number, and a fourth data conversion unit which converts the pixel data D3 to the pixel data signal composed of one bit at the period T0/m.

Abstract: A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied.

Abstract: A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied.

Abstract: The present application discloses a driver having a configuration comprising: a drive transistor for supplying a current of the quantity corresponding to a gate potential, into the element as a driving current; a first switch installed in the path of the driving current passing between the element and the drive transistor, for controlling the flow of the driving current; a second switch for switching between the first state of setting the gate potential of the drive transistor and the second state of keeping the set gate potential; a circuit for supplying a signal for controlling the flow of the driving current in a restricted state to the first switch, for a predetermined period in a period after the starting the supply of the potential for driving the drive transistor from a power source and until start of driving the element in a normal operation; a circuit for supplying a signal for setting the second switch at the first state, to the second switch: and a circuit for interrupting a signal for setting the

Abstract: A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.

Abstract: The present application includes as one invention a display device for displaying images based on video signals, comprising: a timing signal generating circuit for generating a timing signal, a sampling signal generating circuit for generating a sampling signal at the timing corresponding to the timing signal, and a sampling circuit for sampling target signal during a sampling period set by the sampling signal and outputting the sampled target signal, wherein the sampling circuit is connected to the timing signal generating circuit so that test output obtained by sampling a test target signal during the sampling period set by the sampling signal corresponding to a test timing signal generated by the timing signal generating circuit can be input into the timing signal generating circuit, and the timing signal generating circuit controls the relative output timing between the timing signal and the target signal under the control based on the test output input.

Abstract: A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.

Abstract: For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

Abstract: In an integrated circuit, a time-axis expanding circuit is provided in addition to a driver circuit for outputting a signal outside. The time-axis expanding circuit has an equivalent receiver circuit similar to an ordinary receiver circuit, and a D-type flip-flop circuit connected to the equivalent receiver circuit. Input signals from the pins of the time-axis expanding circuit are inputted to the gates of CMOS transistors of the equivalent receiver circuit, and equivalent differential receiving signals outputted from the drains of the CMOS transistors are inputted to the D input terminal of the D-type flip-flop circuit. A measuring clock signal is inputted to the clock input terminal of the D-type flip-flop circuit, and a time-axis-expanded signal is outputted from the Q output terminal of the D-type flip-flop circuit to an output terminal of the time-axis expanding circuit.

Abstract: The application discloses a current signal output circuit. Particularly, the application discloses a constitution including at least a first switch, a first capacitor element and a first transistor in which a first terminal of the first switch is connected to a voltage signal line for providing a voltage signal, a second terminal of the first switch is connected to a first terminal of the first capacitor element, a second terminal of the first capacitor element is connected to a gate electrode of the first transistor and a first main electrode of the first transistor is connected to a first power source.

Abstract: This application discloses a shift register.

Abstract: A first current mirror circuit (M2, M3 and M7) performs its normal operation when a first switch (M2) is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit (M4 and M9) is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor (MB) and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch (M2) and a second switch (M5) are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.

Abstract: A pixel modulation apparatus for converting pixel data D composed of N1 bits to a pixel data signal composed of one bit. The pixel data D is input into the apparatus at a pixel period TO. The apparatus includes a first data conversion unit which converts the pixel data D to pixel data D1 expanded to N2 bits (N2>N1) at the period T0, a second data conversion unit which converts the pixel data D1 to pixel data D2 composed of N3/m bits at a period T0/m, a third data conversion unit which inputs n data from among the pixel data D2 and pixel data Dd2 constituting the pixel data D2 before having the period T0/m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the n data to pixel data D3 composed of N3 bits, including additional data corresponding to the predetermined number, and a fourth data conversion unit which converts the pixel data D3 to the pixel data signal composed of one bit at the period T0/m.