Abstract: An imaging device is provided which includes a solid-state imaging device that includes a plurality of pixels arranged in a form of a two-dimensional (2D) matrix, and outputs pixel signals corresponding to subject light incident on the plurality of pixels, and a plurality of image-acquiring units that acquire the pixel signals output from the solid-state imaging device, and output image data corresponding to the acquired pixel signals, wherein each of the plurality of image-acquiring units acquires pixel signals of one of divisional imaging regions obtained by dividing an imaging region in which all pixels arranged in the solid-state imaging device image the subject light by the number of image-acquiring units, and outputs image data corresponding to the acquired pixel signal of the divisional imaging region as divisional image data.

Abstract: A data processing apparatus may include a data conversion unit for, when converting a plurality of sequentially input data into conversion data of the same bit number as a data bus having a prescribed bit number and sequentially transferring the conversion data. The data conversion unit may include a first data generation unit, a second data generation unit for generating second data obtained by allocating a prescribed second number of input data in the input data not allocated to the first data, to the second bit range and a data coupling unit for coupling the first data and the second data to generate the conversion data having the bit number of the bus width of the data bus.

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: A signal transfer circuit comprising a control signal transfer unit configured to output an access request output signal and a memory address output signal to the arbiter after timings of the access request input signal of the access request and the memory address input signal input from the bus master have been adjusted, and output an access permission output signal, and a data signal transfer unit configured to output each data output signal to the corresponding bus master or the arbiter after a timing of each data input signal of the access request input from the arbiter or the bus master is adjusted, and output a data validity period output signal to the bus master after a timing of a data validity period input signal indicating a period in which each data is valid in the access request input from the arbiter is adjusted.

Abstract: An imaging device is provided which includes a solid-state imaging device that includes a plurality of pixels arranged in a form of a two-dimensional (2D) matrix, and outputs pixel signals corresponding to subject light incident on the plurality of pixels, and a plurality of image-acquiring units that acquire the pixel signals output from the solid-state imaging device, and output image data corresponding to the acquired pixel signals, wherein each of the plurality of image-acquiring units acquires pixel signals of one of divisional imaging regions obtained by dividing an imaging region in which all pixels arranged in the solid-state imaging device image the subject light by the number of image-acquiring units, and outputs image data corresponding to the acquired pixel signal of the divisional imaging region as divisional image data.

Abstract: A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a plurality of input data input sequentially into transfer data having a bit number identical to a predetermined bit number of a data bus and sequentially transferring the converted transfer data. The data conversion unit may include a data generation unit and a first data arrangement changing unit. The first data arrangement changing unit may include a bit change number calculating unit, a bit change number analysis unit, a first data sorting unit, and a data coupling unit.

Abstract: A data processing apparatus includes a data conversion unit for converting a plurality of sequentially input data into transfer data and sequentially transferring the transfer data, arranging the input data in each conversion unit using one transfer data as one transfer unit and a prescribed number of transfer units as one conversion unit, and the data conversion unit includes a first bit division unit for dividing the input data into first and second divided data, a bit comparison unit for comparing first divided data of an n-th time (n is a natural number equal to or more than 1) and an (n+1)-th time, a bit determination unit for determining whether the first divided data is to be inverted based on the determination result to output inversion information, a first bit inversion unit for outputting data selected based on the inversion information, and a first bit coupling unit.

Abstract: A data-processing device includes a plurality of data generation units, a plurality of bit change number calculation units, a bit change number comparison unit, a first data selection unit, and a bit-coupling unit. The data generation unit arranges input data to generate first conversion data based on each prescribed arranging method. The bit change number calculation unit compares values of respective bits in the first conversion data output at the n-th time and the (n+1)-th time by the corresponding data generation unit, and calculates a bit number based on the comparison result as a bit change number. The bit change number comparison unit compares values of the respective bit change numbers, selects the data generation unit, and outputs selection information. The first data selection unit outputs any one first conversion data selected based on the selection information as selection data. Then, the bit-coupling unit couples the selection information.

Abstract: An image display apparatus, which displays a display image obtained by graphically processing an input image stored in an image storage unit connected to a common bus, may include a graphic processing unit that has a function of performing a first and second graphic processes for processing the input image, the graphic processing unit outputting any one of an image obtained by performing the first graphic process on the input image acquired from the image storage unit and an image obtained by performing the second graphic process subsequently to the first graphic process to the image storage unit as a processed image so that the image storage unit stores the processed image, a display processing unit, and a switching control unit that switches a processing unit for performing the second graphic process to any one of the graphic processing unit and the display processing unit based on a predetermined condition.

Abstract: A data processing apparatus includes a data conversion unit for converting a plurality of sequentially input data into transfer data and sequentially transferring the transfer data, arranging the input data in each conversion unit using one transfer data as one transfer unit and a prescribed number of transfer units as one conversion unit, and the data conversion unit includes a first bit division unit for dividing the input data into first and second divided data, a bit comparison unit for comparing first divided data of an n-th time (n is a natural number equal to or more than 1) and an (n+1)-th time, a bit determination unit for determining whether the first divided data is to be inverted based on the determination result to output inversion information, a first bit inversion unit for outputting data selected based on the inversion information, and a first bit coupling unit.

Abstract: A data-processing device includes a plurality of data generation units, a plurality of bit change number calculation units, a bit change number comparison unit, a first data selection unit, and a bit-coupling unit. The data generation unit arranges input data to generate first conversion data based on each prescribed arranging method. The bit change number calculation unit compares values of respective bits in the first conversion data output at the n-th time and the (n+1)-th time by the corresponding data generation unit, and calculates a bit number based on the comparison result as a bit change number. The bit change number comparison unit compares values of the respective bit change numbers, selects the data generation unit, and outputs selection information. The first data selection unit outputs any one first conversion data selected based on the selection information as selection data. Then, the bit-coupling unit couples the selection information.

Abstract: A data processing apparatus may include a data conversion unit for, when converting a plurality of sequentially input data into conversion data of the same bit number as a data bus having a prescribed bit number and sequentially transferring the conversion data, arranging the input data in each conversion unit using the conversion data as one transfer unit and a prescribed number of transfer units as one conversion unit. The data conversion unit may include a first data generation unit, a second data generation unit for generating second data obtained by allocating a prescribed second number of input data in the input data not allocated to the first data, to the second bit range and a data coupling unit for coupling the first data and the second data to generate the conversion data having the bit number of the bus width of the data bus.

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a plurality of input data input sequentially into transfer data having a bit number identical to a predetermined bit number of a data bus and sequentially transferring the converted transfer data. The data conversion unit may include a data generation unit and a first data arrangement changing unit. The first data arrangement changing unit may include a bit change number calculating unit, a bit change number analysis unit, a first data sorting unit, and a data coupling unit.

Abstract: Disclosed herein is an LSI apparatus having a CPU and a plurality of functional blocks for controlling an external equipment, the plurality of functional blocks sharing one external terminal connected to the external equipment, including: a mode register having a flag information set by the CPU indicating validity or invalidity of each functional block; a selector for switching the connection between each functional block and the external terminal; and a switch controller retaining a priority sequence among each functional block, for controlling switching of the selector based on the priority sequence and the flag information set at the mode register.

Abstract: Disclosed herein is an LSI apparatus having a CPU and a plurality of functional blocks for controlling an external equipment, th plurality of functional blocks sharing one external terminal connected to the external equipment, including: a mode register having a flag information set by the CPU indicating validity or invalidity of each functional block; a selector for switching the connection between each functional block and the external terminal; and a switch controller retaining a priority sequence among each functional block, for controlling switching of the selector based on the priority sequence and the flag information set at the mode register.