Patents by Inventor Masamitsu Kishigami

Masamitsu Kishigami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5689352
    Abstract: A plurality of conductive lines are formed on a lower base plate. One surface of the lower base plate is divided into a first portion which is to be formed into a lower substrate, and a second portion. The first portion includes a first area which is to be covered with an upper substrate, and a second area. The conductive lines are extended from the first area of the first portion to the second portion through the second area of the first portion. A connecting pattern is formed on the second portion, and is connected to each of the conductive lines. Thereafter, an orientation film is formed on the first area of the first portion. Then, the surface of an orientation film is rubbed in an orientation process. During the orientation process, electric charges which are generated in each of the conductive lines by friction, flow to the connecting pattern immediately. Therefore, the conductive lines and the orientation film are protected from the electric charges, and damage is avoided.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: November 18, 1997
    Assignee: Casio Computer Co., Ltd.
    Inventor: Masamitsu Kishigami
  • Patent number: 5467210
    Abstract: A board-shaped lower glass substrate of a liquid crystal display (LCD) device has a size larger than a board-shaped upper glass substrate of the LCD device. An edge of part of the lower glass substrate extending beyond a corresponding edge of the upper glass substrate has a plurality of IC chips mounted thereon. Output pads connected to output electrodes of the IC chips are mounted to that edge of the lower glass substrate on the side of the display area of the LCD device. Input pads connected to input electrodes of the IC chips are mounted to that edge of the lower glass substrate on the side remote from the display area. Wiring patterns formed on that edge of the lower glass substrate and connected to the input and output pads extend along the direction of an arrangement of IC the chips. One end of each wiring pattern is positioned at an edge of the lower glass substrate.
    Type: Grant
    Filed: February 7, 1994
    Date of Patent: November 14, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventor: Masamitsu Kishigami