Patents by Inventor Masamitsu Matsuura
Masamitsu Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11942384Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.Type: GrantFiled: October 29, 2021Date of Patent: March 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
-
Patent number: 11923320Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.Type: GrantFiled: December 31, 2020Date of Patent: March 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
-
Patent number: 11848244Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.Type: GrantFiled: September 30, 2021Date of Patent: December 19, 2023Assignee: Texas Instruments IncorporatedInventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya
-
Publication number: 20230396230Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Inventors: Anindya PODDAR, Hau NGUYEN, Masamitsu MATSUURA
-
Publication number: 20230275007Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Makoto SHIBUYA, Masamitsu Matsuura, Kengo Aoya, Anindya Poddar
-
Patent number: 11736085Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.Type: GrantFiled: August 25, 2020Date of Patent: August 22, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anindya Poddar, Hau Nguyen, Masamitsu Matsuura
-
Publication number: 20230137762Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
-
Publication number: 20230095630Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Makoto SHIBUYA, Masamitsu MATSUURA, Kengo AOYA
-
Publication number: 20230068748Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for receiving a semiconductor die, and having conductive leads spaced from the die pad; a semiconductor die mounted on the die pad, the semiconductor die having bond pads on an active surface configured for making electrical connections; electrical connections coupling the bond pads of the semiconductor die to the conductive leads; mold compound covering a portion of the package substrate, the semiconductor die, and the electrical connections, with the leads extending through the mold compound and having end portions exposed from the mold compound; and the leads having a first portion with a first width and extending with the first width from the mold compound to a second portion having a second width that greater than the first width.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventor: Masamitsu Matsuura
-
Publication number: 20230005881Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Anindya Poddar, Mahmud Chowdhury, Hau Nguyen, Masamitsu Matsuura, Ting-Ta Yen
-
Patent number: 11410875Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).Type: GrantFiled: December 19, 2018Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
-
Publication number: 20220208689Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Tomoko NOGUCHI, Mutsumi MASUMOTO, Kengo AOYA, Masamitsu MATSUURA
-
Publication number: 20220069795Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Inventors: Anindya PODDAR, Hau NGUYEN, Masamitsu MATSUURA
-
Patent number: 11183441Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.Type: GrantFiled: March 3, 2020Date of Patent: November 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
-
Patent number: 11158595Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.Type: GrantFiled: July 6, 2018Date of Patent: October 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
-
Publication number: 20210125959Abstract: In some examples, a wafer chip scale package (WCSP) comprises a die; multiple electrically conductive terminals coupled to a first surface of the die; and a metal covering abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.Type: ApplicationFiled: October 24, 2019Publication date: April 29, 2021Inventors: Masamitsu MATSUURA, Kengo AOYA, Mutsumi MASUMOTO
-
Publication number: 20210111136Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.Type: ApplicationFiled: January 10, 2020Publication date: April 15, 2021Inventors: Masamitsu Matsuura, Daiki Komatsu
-
Patent number: 10879144Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.Type: GrantFiled: August 14, 2019Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami, Hideaki Matsunaga
-
Publication number: 20200203219Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
-
Publication number: 20200203249Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar