Abstract: An LC resonance element (10) includes a dielectric film (12), a common electrode (11) formed of a thin-film conductor on a lower surface (12D) of the dielectric film, a first capacitor (C1) and a second capacitor (C2) that are connected in series via the common electrode (11) and constitute a thin-film capacitor (TC), first and second external connection terminals (14A, 14B) formed on an upper surface (12U) of the dielectric film, a thin-film conductive wire (16) constituting a thin-film inductor (TL), a first upper electrode (13A) of the first capacitor formed on the upper surface (12U), and a second upper electrode (13B) of the second capacitor formed on the upper surface (12U). The thin-film conductive wire (16) is formed in a region (R2) located on the upper surface (12U) of the dielectric film and outside the common electrode (11) in plan view.

Abstract: An LC resonance element (10) includes a dielectric film (12), a common electrode (11) formed of a thin-film conductor on a lower surface (12D) of the dielectric film, a first capacitor (C1) and a second capacitor (C2) that are connected in series via the common electrode (11) and constitute a thin-film capacitor (TC), first and second external connection terminals (14A, 14B) formed on an upper surface (12U) of the dielectric film, a thin-film conductive wire (16) constituting a thin-film inductor (TL), a first upper electrode (13A) of the first capacitor formed on the upper surface (12U), and a second upper electrode (13B) of the second capacitor formed on the upper surface (12U). The thin-film conductive wire (16) is formed in a region (R2) located on the upper surface (12U) of the dielectric film and outside the common electrode (11) in plan view.

Abstract: A multi-layered circuit board includes a first insulating layer, a second insulating layer, and a sheet capacitor that is located between the first insulating layer and the second insulating layer. The sheet capacitor includes a pair of electrodes that sandwich a dielectric. Lead wirings continue to the electrodes, respectively. The lead wirings are disposed on an opposite side of the first or the second insulating layer with respect to the sheet capacitor to overlap the electrodes when viewed from a stacking direction of the multi-layered circuit board. Because the lead wirings are arranged to overlap the electrodes in the stacking direction of the multi-layered circuit board, an ESL of the sheet capacitor is maintained low.

Abstract: A thin film capacitor in a redistribution layer of a semiconductor device including a semiconductor chip. The thin film capacitor includes a capacitor body including a first electrode, a dielectric on the first electrode, and a second electrode on the dielectric, and an adhesive portion disposed on a lower surface of the first electrode and used for attaching the thin film capacitor to a protective film of the semiconductor chip. A total of a thickness of the capacitor body and a thickness of the adhesive portion is 20 ?m or smaller.

Abstract: A multi-layered circuit board includes a first insulating layer, a second insulating layer, and a sheet capacitor that is located between the first insulating layer and the second insulating layer. The sheet capacitor includes a pair of electrodes that sandwich a dielectric. Lead wirings continue to the electrodes, respectively. The lead wirings are disposed on an opposite side of the first or the second insulating layer with respect to the sheet capacitor to overlap the electrodes when viewed from a stacking direction of the multi-layered circuit board. Because the lead wirings are arranged to overlap the electrodes in the stacking direction of the multi-layered circuit board, an ESL of the sheet capacitor is maintained low.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.