Abstract: There is disclosed a semiconductor device including a plurality of P well regions (4) and a P well region (41) insulated from each other by a plurality of trench isolating layers (10) formed regularly in predetermined spaced relation with each other and having the same depth. The outermost P well region (41) isolatedly formed externally of an outermost trench isolating layer (10A) is made as deep as the trench isolating layers (10) and, accordingly, is made deeper than the P well regions (4) except the outermost P well region (41). This provides for the alleviation of the electric field concentration generated in the bottom edge of the outermost isolating layer of trench structure, thereby achieving the semiconductor device having an improved device breakdown voltage and a method of fabricating the same.

Abstract: A base layer is formed as first and second base layers through two steps, so that only an upper base layer (second base layer) can be easily set in high impurity concentration dissimilarly to conventional one. As the result, a JFET effect can be suppressed. Further, first and second well regions are formed for the first and second base layer, respectively, to be coupled with each other to form a single well region, so that a lower well region (first well region) can be easily set higher in impurity concentration than an upper well region (second well region). As the result, a latch-up phenomenon can be prevented.

Abstract: An n-buffer layer and an n.sup.- -base layer are formed on a p.sup.+ -anode layer. A p-base layer is formed on the n.sup.- -base layer. The p-base layer has a p-type impurity layer protruding into n.sup.- -base layer. An n-cathode layer, an n.sup.+ -cathode layer and a P+-impurity layer are formed on p-base layer. First trenches are formed through p.sup.+ -impurity later, n-cathode layer and p-base layer. On-gates are formed in the first trenches. Second trenches are formed through p.sup.+ -impurity layer and n-cathode layer with their bottom surfaces located in p-type impurity layer. Off-gates are formed in the second trenches. First and second trenches are preferably formed alternately. Thereby, a voltage-driven thyristor has improved turn-on and turn-off characteristics and a high reliability.

Abstract: There is disclosed a semiconductor device having a vertical channel MOS gate structure wherein grooves (40) are formed from the top surface of source regions (5) through a body (3) into an N diffusion region (2) and wherein buried gate electrodes (4) fill an inner part of said grooves (40) which is in face-to-face relation to the N diffusion region (2) across gate oxide films (13) while buried oxide films (15) including diffusion source impurities fill an inner part thereof which is in face-to-face relation to the source regions (5). The impurity concentration of the source regions (5) is distributed uniformly in the vertical direction of the grooves (40) and decreases lateraly away from the grooves (40). A current flows through the source region along the grooves and a resistance thereagainst is held small in an ON-state. The grooves may be formed with narrow spacing. The size reduction and high integration of the semiconductor device are achieved as well as reduction in ON-resistance.

Abstract: In a static induction type switching device having gate regions buried in a semiconductor substrate, the gate regions are formed by polysilicon layers and diffusion layers which can be formed by diffusion from the polysilicon layers serving as diffusion sources. Therefore, dimensional accuracy, electric properties etc. can be improved such that channel regions can be accurately defined between the gate regions in the semiconductor substrate, and the channel regions can be formed through use of the semiconductor substrate etc.

Abstract: An insulated gate bipolar transistor has a P-type well region (3) which is partially formed in a surface of an N.sup.- -type epitaxial layer (2) formed on a P.sup.+ -type semiconductor substrate (1). A trench (14) is formed in a central portion of the P-type well region (3), and an N.sup.+ -type emitter region (4) is formed in a surface of the P-type well region (3) around the trench (14). The N.sup.+ -type emitter region (4) is provided thereon with an emitter electrode (7), which is extended into the trench (14) as a conductive layer to electrically connect a deep portion of the P-type well region (3) with the N.sup.+ -type emitter region (4). Thus, vertical resistance of the P-type well region (3) is reduced, whereby base-to-emitter resistance of an NPN transistor defined by the N.sup.- -type epitaxial layer (2), the P-type well region (3) and the N.sup.+ -type emitter region (4 ) is reduced to prevent a latch-up of a parasitic PNPN thyristor.

Abstract: In a static induction type switching device having gate regions buried in a semiconductor substrate, the gate regions are formed by polysilicon layers and diffusion layers which can be formed by diffusion from the polysilicon layers serving as diffusion sources. Therefore, dimensional accuracy, electric properties etc. can be improved such that channel regions can be accurately defined between the gate regions in the semiconductor substrate, and the channel regions can be formed through use of the semiconductor substrate etc.

Abstract: An insulated gate bipolar transistor has a P-type well region (3) which is partially formed in a surface of an N.sup.- -type epitaxial layer (2) formed on a P.sup.+ -type semiconductor substrate (1). A trench (14) is formed in a central portion of the P-type well region (3), and an N.sup.+ -type emitter region (4) is formed in a surface of the P-type well region (3) around the trench (14). The N.sup.+ -type emitter region (4) is provided thereon with an emitter electrode (7), which is extended into the trench (14) as a conductive layer to electrically connect a deep portion of the P-type well region (3) with the N.sup.+ -type emitter region (4). Thus, vertical resistance of the P-type well region (3) is reduced, whereby base-to-emitter resistance of an NPN transistor defined by the N.sup.- -type epitaxial layer (2), the P-type well region (3) and the N.sup.+ -type emitter region (4 ) is reduced to prevent a latch-up of a parasitic PNPN thyristor.

Abstract: An N drift region (42) is provided in its surface with a P.sup.+ well region (43) of a square ring shape and a P region (51) formed in the center of the square ring. The P region (51) is relatively low in impurity concentration and relatively small in thickness while the P.sup.+ well region (43) is relatively high in impurity concentration and relatively large in thickness. The P region (51) of low impurity concentration is lower in built-in voltage than P.sup.+ well region (43) of high impurity concentration, so that most part of a forward current of a diode consisting of the N drift region (42) and the P.sup.+ well and P regions (43, 51) can flow through the P region (51). Because of the low impurity concentration and small thickness of the P region (51), the rate of minority carriers in the forward current is low. Thus, a reverse recovery time of the diode can be shortened.

Abstract: A base layer is formed as first and second base layers through two steps, so that only an upper base layer (second base layer) can be easily set in high impurity concentration dissimilarly to conventional one. As the result, a JFET effect can be suppressed. Further, first and second well regions are formed for the first and second base layer, respectively, to be coupled with each other to form a single well region, so that a lower well region (first well region) can be easily set higher in impurity concentration than an upper well region (second well region). As the result, a latch-up phenomenon can be prevented.