Abstract: According to one embodiment, a mask pattern verification method includes: calculating mask pattern data; calculating an optical image and a resist image; calculating a first feature amount and a second feature amount, using a plurality of algorithms; in each of the plurality of algorithms, comparing the first feature amount with a first threshold, and detecting a critical point candidate in a first pattern; in each of the plurality of algorithms, comparing the second feature amount with a second threshold, and detecting a critical point in the first pattern; and selecting at least one of the plurality of algorithms, and displaying a detection result of the critical point corresponding to a selected algorithm.

Abstract: According to one embodiment, a mask pattern verification method includes: calculating mask pattern data; calculating an optical image and a resist image; calculating a first feature amount and a second feature amount, using a plurality of algorithms; in each of the plurality of algorithms, comparing the first feature amount with a first threshold, and detecting a critical point candidate in a first pattern; in each of the plurality of algorithms, comparing the second feature amount with a second threshold, and detecting a critical point in the first pattern; and selecting at least one of the plurality of algorithms, and displaying a detection result of the critical point corresponding to a selected algorithm.

Abstract: According to one embodiment, a first auxiliary pattern is arranged at a corner of a mask pattern, an arrangement position of a second auxiliary pattern is calculated based on an opening angle of a resist pattern to which the mask pattern is transferred, and the second auxiliary pattern is arranged at the arrangement position.

Abstract: A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Abstract: A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Abstract: A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

Abstract: According to one embodiment, an evaluating apparatus includes a resist-pattern-data acquiring unit and an evaluating unit. The resist-pattern-data acquiring unit acquires resist pattern data having a plurality of feature values including at least two among a hole diameter measured concerning a pattern for hole formation in the resist pattern, an aspect ratio of the hole diameter, and a difference of hole diameters at a plurality of signal thresholds. The evaluating unit calculates an evaluation value using an evaluation function for evaluating whether a hole pattern formed on a processing target by using the pattern for hole formation is unopened and the resist pattern data and evaluates presence or absence of a risk that the hole pattern is unopened.