Patents by Inventor Masanori Akatsuka

Masanori Akatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7700394
    Abstract: There is obtained a silicon wafer which has a large diameter, where no slip generated therein in a wide range of a density of oxygen precipitates even though a heat treatment such as SLA or FLA is applied thereto, and which has high strength. First, by inputting as input parameters combinations of a plurality of types of oxygen concentrations and thermal histories set for manufacture of a silicon wafer, a Fokker-Planck equation is solved to calculate each of a diagonal length L and a density D of oxygen precipitates in the wafer after a heat treatment step to form the oxygen precipitates (11) and immediately before a heat treatment step of a device manufacturing process is calculated.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: April 20, 2010
    Assignee: Sumco Corporation
    Inventors: Shinsuke Sadamitsu, Wataru Sugimura, Masanori Akatsuka, Masataka Hourai
  • Publication number: 20080118424
    Abstract: There is obtained a silicon wafer which has a large diameter, where no slip generated therein in a wide range of a density of oxygen precipitates even though a heat treatment such as SLA or FLA is applied thereto, and which has high strength. First, by inputting as input parameters combinations of a plurality of types of oxygen concentrations and thermal histories set for manufacture of a silicon wafer a Fokker-Planck equation is solved to calculate each of a diagonal length L and a density D of oxygen precipitates in the wafer after a heat treatment step to form the oxygen precipitates (11) and immediately before a heat treatment step of a device manufacturing process is calculated.
    Type: Application
    Filed: June 21, 2005
    Publication date: May 22, 2008
    Inventors: Shinsuke Sadamitsu, Wataru Sugimura, Masanori Akatsuka, Masataka Hourai
  • Publication number: 20050158921
    Abstract: An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.
    Type: Application
    Filed: February 16, 2005
    Publication date: July 21, 2005
    Inventors: Masanori Akatsuka, Naoshi Adachi
  • Patent number: 6875643
    Abstract: An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: April 5, 2005
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Masanori Akatsuka, Naoshi Adachi
  • Publication number: 20040232490
    Abstract: An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.
    Type: Application
    Filed: December 22, 2003
    Publication date: November 25, 2004
    Inventors: Masanori Akatsuka, Naoshi Adachi
  • Patent number: 6599816
    Abstract: A method is designed to manufacture a silicon epitaxial wafer exhibiting sufficient gettering capability from the initial stage of the device process. Specifically, the method is to manufacture the silicon wafer with a nitrogen concentration of at least 1×1012 atoms/cm3 and an oxygen concentration of 10˜18×1017 atoms/cm3 by annealing at a temperature of 800˜1,100° C. after epitaxial growth treatment, satisfying the following equation (a), t≧33−((T−800)/100)  (a) wherein T(° C.) is temperature, and t(hr) is time, thereby manufacturing a high yield semiconductor device.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: July 29, 2003
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Kouji Sueoka, Masanori Akatsuka, Yasuo Koike
  • Publication number: 20010021574
    Abstract: A method is designed to manufacture a silicon epitaxial wafer exhibiting sufficient gettering capability from the initial stage of the device process. Specifically, the method is to manufacture the silicon wafer with a nitrogen concentration of at least 1×1012 atoms/cm3 and an oxygen concentration of 10˜18×1017 atoms/cm3 by annealing at a temperature of 800 ˜1,100° C.
    Type: Application
    Filed: March 8, 2001
    Publication date: September 13, 2001
    Applicant: Sumitomo Metal Industries, Ltd.
    Inventors: Kouji Sueoka, Masanori Akatsuka, Yasuo Koike
  • Patent number: 5587793
    Abstract: A sample is placed between a circular polarizer and an analyzer in an optical path between a monochromatic light source and a two-dimensional optical receiver. Parallel beams emitted from the monochromatic light source are converted into circularly polarized light by the circular polarizer. After transmitting the sample, the light is guided to the analyzer. While rotating the analyzer about the axis of the beams, image data are detected by optical receiver at a step of a regular rotation angle, and the detected image data are sampled to be sent to an image processing device in the next stage. On the basis of the image data, an operation is conducted on each pixel to obtain a relative phase difference due to birefringence of the sample, the two-dimensional birefringence distribution including the sign of the relative phase difference, and also the principal axis direction.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 24, 1996
    Assignees: Sadao Nakai, Institute for Laser Technology, Fuji Electric Co., Ltd.
    Inventors: Sadao Nakai, Yasukazu Izawa, Masanobu Yamanaka, Masato Ohmi, Masanori Akatsuka, Chiyoe Yamanaka, Yoshiyuki Yonezawa