Abstract: According to one embodiment, the insulating layer is provided on the terrace portions. The plurality of contact portions extend through the insulating layer in the stacking direction and contact the terrace portions. The second columnar portion extends through the insulating layer and through the second stacked portion in the stacking direction, and includes a second semiconductor body contacting the first semiconductor region. The first insulating portion divides the first semiconductor region in the first direction. The first insulating portion is provided under a boundary portion between the first stacked portion and the second stacked portion.

Abstract: According to one embodiment, the insulating layer is provided on the terrace portions. The plurality of contact portions extend through the insulating layer in the stacking direction and contact the terrace portions. The second columnar portion extends through the insulating layer and through the second stacked portion in the stacking direction, and includes a second semiconductor body contacting the first semiconductor region. The first insulating portion divides the first semiconductor region in the first direction. The first insulating portion is provided under a boundary portion between the first stacked portion and the second stacked portion.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.

Abstract: In one embodiment, a semiconductor device includes a substrate; a gate insulating film; first trenches in a cell array region; first embedded insulating films in the first trenches; second trenches in a peripheral circuit region; second embedded insulating films in the second trenches; a third trench in an isolation region; a third embedded insulating film in the third trench; gate structures; and inter-gate insulating films between the gate structures covering the first, second and third embedded insulating films. An upper surface of the third embedded insulating film covered with the inter-gate insulating film is substantially flat. Upper surfaces of the first, second, and third embedded insulating films are higher than an upper surface of the gate insulating film. The upper surfaces of the first and third embedded insulating films are lower than the upper surfaces of the second embedded insulating films.

Abstract: A plurality of NAND cells are arranged in a cell array. In each of the NAND cells, a pair of selection gate transistors is connected in series to a plurality of memory cell transistors. An inter-gate connection trench is formed in an insulating film between layers of stacked gates of the selection gate transistors. The stacked gates are electrically connected to each other. At an end part of the cell array in the row direction, an STI area is formed, and dummy NAND cells are formed at an end part in the row direction. A dummy selection gate transistor is connected in series to a plurality of dummy memory cell transistors. No inter-gate connection trench is present in an insulating film between layers of stacked gates of the dummy selection gate transistor, and the stacked gates of the dummy selection gate transistor are not electrically connected to each other.

Abstract: In one embodiment, a semiconductor device includes a substrate; a gate insulating film; first trenches in a cell array region; first embedded insulating films in the first trenches; second trenches in a peripheral circuit region; second embedded insulating films in the second trenches; a third trench in an isolation region; a third embedded insulating film in the third trench; gate structures; and inter-gate insulating films between the gate structures covering the first, second and third embedded insulating films. An upper surface of the third embedded insulating film covered with the inter-gate insulating film is substantially flat. Upper surfaces of the first, second, and third embedded insulating films are higher than an upper surface of the gate insulating film. The upper surfaces of the first and third embedded insulating films are lower than the upper surfaces of the second embedded insulating films.

Abstract: A plurality of NAND cells are arranged in a cell array. In each of the NAND cells, a pair of selection gate transistors is connected in series to a plurality of memory cell transistors. An inter-gate connection trench is formed in an insulating film between layers of stacked gates of the selection gate transistors. The stacked gates are electrically connected to each other. At an end part of the cell array in the row direction, an STI area is formed, and dummy NAND cells are formed at an end part in the row direction. A dummy selection gate transistor is connected in series to a plurality of dummy memory cell transistors. No inter-gate connection trench is present in an insulating film between layers of stacked gates of the dummy selection gate transistor, and the stacked gates of the dummy selection gate transistor are not electrically connected to each other.

Abstract: A transcriptional inhibitor for human K-ras gene which comprises one or more proteins selected from the group consisting of a protein having the amino acid sequence represented by SEQ ID NO:1, a protein having an amino acid sequence derived from the amino acid sequence represented by SEQ ID NO:1 by substitution, deletion or addition of one to several amino acids and having an activity of inhibiting the transcription of human K-ras gene, and partial fragment proteins thereof having an activity of inhibiting the transcription of human K-ras gene. This transcriptional inhibitor for human K-ras gene specifically inhibits the transcription and expression of K-ras gene, which is an oncogene, in a human cancer cell. Thus, it can inhibit the proliferation of cancer cells and induce the reversion of cancer cells into normal cells, which makes it usable as an anticancer agent with little side effects on normal cells.

Abstract: The present invention is directed to recombinant the IL-21R.beta. chain or fragments thereof, cDNA coding therefore, vectors containing said cDNA, hosts transfected by said vectors, and monoclonal antibodies to said recombinant IL-2R.beta. or fragments thereof.

Abstract: The present invention is directed to recombinant IL-2R.mu. protein or fragments thereof, cDNA coding therefore, vectors containing this cDNA, hosts transfected by these vectors, and monocional antibodies to the encoded recombinant IL-2R.mu. protein or fragments thereof.