Abstract: A multiprocessor system includes a plurality of processors, each including a task scheduler that determines a task execution order of tasks in a task set to be executed by the processors within a task period which is defined as a period in repeated execution of the task sets; and a scheduler management device having a command unit configured to issue a command for at least one of the task schedulers to change the task execution order, wherein each of the at least one of the task schedulers, when receiving the command from the command unit, changes the task execution order of the corresponding processor.

Abstract: A computer system which significantly improves responsiveness to a sleep request includes: a processor device switching between an execution mode and a suspension mode; and an access controlling unit accessing a functional block in response to a command request received from the processor device, wherein, in response to a sleep request signal received from the external device, the processor device responds with a sleep response signal and asserts a suspension notification signal indicating a switch to the suspension mode, and the access controlling unit: masks an input of a further command request after receiving the command request from the processor device, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal; masks an input of a command request in the case where the processor device has not outputted the command request; and removes the mask when the suspension notification signal is negated.

Abstract: A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) and a parallel processor controller which switches threads in each PE. The parallel processor controller includes a plurality of execution order registers which hold, for each processor element, an execution order of threads to be executed; a plurality of counters which count an execution time for a thread that is being executed by each processor element and generate a timeout signal when the counted time reaches a limit assigned to the thread; and a thread execution scheduler which switches the thread that is being executed to the thread to be executed by each processor element based on an execution order held in the execution order register and the timeout signal.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A virtual multiprocessor according to the present invention includes: one or more processors that execute programs while switching between the programs at each of assigned times; a scheduling unit that performs scheduling that determines execution sequence of the programs and the one or more processors that are to execute one or more of the programs, wherein the scheduling unit performs the scheduling at a timing dependent on an assigned time associated with a corresponding one of the programs being executed by the one or more processors, in the case where a first mode is set, and performs the scheduling at a timing not dependent on the assigned time so that at least one of the one or more processors does not execute the programs, in the case where a second mode is set.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A computer system which significantly improves responsiveness to a sleep request includes: a processor device switching between an execution mode and a suspension mode; and an access controlling unit accessing a functional block in response to a command request received from the processor device, wherein, in response to a sleep request signal received from the external device, the processor device responds with a sleep response signal and asserts a suspension notification signal indicating a switch to the suspension mode, and the access controlling unit: masks an input of a further command request after receiving the command request from the processor device, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal; masks an input of a command request in the case where the processor device has not outputted the command request; and removes the mask when the suspension notification signal is negated.

Abstract: A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) 101 to 103, and a parallel processor control unit 200, which switches threads in each PE, and the parallel processor control unit 200 includes: a plurality of execution order registers, which hold, for each processor element, an execution order of threads to be executed; a plurality of counters 230, which count an execution time for a thread that is being executed by each processor element and generate a timeout signal when the counted time reaches a limit assigned to the thread; and a thread execution scheduler unit 210, which switches the thread that is being executed to the thread to be executed by each processor element based on the execution order held in said execution order register and the timeout signal.

Abstract: The data transfer device for transferring data between a system bus and a local memory having a frame buffer region and a general region includes an interface section and a data processor. The interface section generates a transfer parameter for accessing one of the frame buffer region and the general region based on control data for controlling data transfer sent from the system bus and outputs the generated transfer parameter, in addition to transferring data to/from the system bus. The data processor generates an address of data to be transferred in the local memory according to the transfer parameter, and transfers data to/from the local memory using the generated address, in addition to transferring data to/from the interface section.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: The data transfer device for transferring data between a system bus and a local memory having a frame buffer region and a general region includes an interface section and a data processor. The interface section generates a transfer parameter for accessing one of the frame buffer region and the general region based on control data for controlling data transfer sent from the system bus and outputs the generated transfer parameter, in addition to transferring data to/from the system bus. The data processor generates an address of data to be transferred in the local memory according to the transfer parameter, and transfers data to/from the local memory using the generated address, in addition to transferring data to/from the interface section.