Abstract: According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.

Abstract: According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a signal supply controller to supply a signal, which allows a level of a resistance value of one of the first and second switching elements to be a predetermined level, to the elements via shared signal wire, and to set a current flowing through the higher-potential side terminal in the one of the first and second switching elements to a value which causes the level of the resistance value to be the predetermined level. In a state where the level of the resistance value of the one of the first and second switching elements is set to the predetermined level, another of the first and second switching elements is brought into a conducting state.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a signal supply controller to supply a signal, which allows a level of a resistance value of one of the first and second switching elements to be a predetermined level, to the elements via shared signal wire, and to set a current flowing through the higher-potential side terminal in the one of the first and second switching elements to a value which causes the level of the resistance value to be the predetermined level. In a state where the level of the resistance value of the one of the first and second switching elements is set to the predetermined level, another of the first and second switching elements is brought into a conducting state.

Abstract: A semiconductor device of an embodiment of the invention has a package substrate, and a semiconductor chip mounted on the package substrate. The semiconductor chip has an output section, and a filter section for decreasing the electromagnetic noise generated from the data communication path. The output section outputs a data signal into the data communication path, and has a buffer amplifier section for compensating the data signal.

Abstract: A semiconductor device of an embodiment of the invention has a package substrate, and a semiconductor chip mounted on the package substrate. The semiconductor chip has an output section, and a filter section for decreasing the electromagnetic noise generated from the data communication path. The output section outputs a data signal into the data communication path, and has a buffer amplifier section for compensating the data signal.

Abstract: An oscillation circuit comprises a ring oscillator configured to have at least an odd number of stages of inverters, and a frequency multiplier section configured to output as a multiplied output, an exclusive OR of signals taken out from the inverters at least at two stages of the ring oscillator.

Abstract: A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

Abstract: An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.

Abstract: A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

Abstract: A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal.

Abstract: A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circu

Abstract: A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circu

Abstract: An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.

Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor(N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

Abstract: A power supply terminal is supplied with a power supply potential. A reference terminal is supplied with a reference potential. First and second p-channel MOS transistor, and first and second n-channel MOS transistor each has a gate, a source, a drain, and a back gate. The gate, source and back gate of the first pMOS transistor, the back gate of the second pMOS transistor, and the gate and drain of the second nMOS transistor are connected to the power supply terminal. The source of the second pMOS transistor is connected to the drain of the first pMOS transistor. The gate and drain of the second pMOS transistor, the gate, source and back gate of the first nMOS transistor, and the back gate of the second nMOS transistor are connected to the reference terminal. The source of the second nMOS transistor is connected to the drain of the first nMOS transistor.

Abstract: A temperature detector circuit for converting a forward drop voltage of a diode to digital data by means of an AD converter is provided. In order to restrict an occurrence of an output error caused by dispersion in diode manufacture, correction data according to digital data obtained by the AD converter is stored in advance in a storage circuit under a known arbitrary temperature condition, and subtraction is performed between digital data obtained by the AD converter under an unknown temperature condition and correction data read from a storage circuit, thereby to perform correction.

Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

Abstract: Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to the output terminal while an power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to the pn-junction provided between a drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.