Abstract: A nonvolatile storage device according to the invention is a nonvolatile storage device into which data is inputted from an external device on a sector unit, and includes: a main memory which is nonvolatile and in which data is written on a page unit, the page unit being larger than the sector unit; an auxiliary memory which holds at least a single page worth of the input data; a memory judging unit that judges whether or not data held in the auxiliary memory is equal to or larger than data of the page unit; and a memory control unit that writes, in a new page of the main memory on the page unit, the data held in the auxiliary memory when the memory judgment unit judges that the data held in the auxiliary memory is equal to or larger than data of the page unit.

Abstract: A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Abstract: At least one transistor (MPX) is connected between a plurality of word line driving element circuits formed by using CMOS inverters (MP0 and MN0, etc.) and a source potential (Vcc). This transistor (MPX) is independently controlled by a control signal (DECENB) separate from control signals (AB-0 to AB-n) of the word line driving element circuits and has both a through current preventing function by adjusting timing and a peak current reducing function by limiting an electric current. Even when all word lines (SWL0 to SWLn) are driven at the same time, the electric current is limited and the peak current is suppressed.

Abstract: A data mask section outputs memory data read from a memory array unit for a predetermined time period that is shifted from an edge timing of a clock signal, while a microcomputer takes in the data output from the data mask section at the edge timing of the clock signal. Thus, the microcomputer is capable of appropriately taking in the memory data only when the frequency of the clock signal is within a predetermined range, and accordingly, it is difficult to fraudulently obtain the memory data. Furthermore, the data mask section may output random data, or the like, during a time period other than the predetermined time period. In such a case, it is difficult to analyze the memory data, and the confidentiality of the memory data is improved.

Abstract: A memory rewriting system for a vehicle controller is provided. The system comprises a vehicle controller and an external rewriting device. A vehicle controller comprises a rewritable memory storing first security data. The first security data is used to determine whether rewriting to the rewritable memory is permitted. The rewriting device transfers new security data to the vehicle controller. The vehicle controller deletes the first security data and writes the new security data into the rewritable memory. Rewriting the new security data is performed by a program stored in a non-rewritable memory. Thus, the security data that is used to determine whether rewriting to the rewitable memory is permitted is rewritten with the new security data. Therefore, if the existing security data stored in the vehicle controller is invalidated, the security feature of the vehicle can be recovered. The vehicle may includes an anti-theft system.

Abstract: A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Abstract: A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Abstract: The rewriting device for rewriting data stored in a memory of a vehicle controller with new data is provided. The rewriting device is capable of communicating with the vehicle controller. When deleting or writing operation on the memory is not being performed, the rewriting device determines that communication between the rewriting device and the vehicle controller is offline if no response from the vehicle controller within a first determination time. When deleting operation or writing operation on the memory is being performed, the determination of offline is prohibited until a second determination time has elapsed. The second determination time is greater than the first determination time. It is preferable that the second determination time for deleting operation is the time necessary to delete the data stored in the memory, and that the second determination time for writing operation is the time necessary to write the new data into the memory.

Abstract: A vehicle controller comprises a first buffer for storing at least one data block, a second buffer for storing at least one data block, and a rewritable non-volatile memory for storing information for controlling a vehicle. The controller receives a data block from an external rewriting device to store it in the first buffer. The data block stored in the first buffer is transferred to the second buffer. The data block stored in the second buffer is written into the memory. When a first data block is written into the memory, a subsequent data block is received. Thus, the time required to rewrite data stored in the nonvolatile memory is reduced.

Abstract: The rewriting system for rewriting data stored in a memory of a vehicle controller with new data is provided. The rewriting device is capable of communicating with the vehicle controller. The rewriting device enters a waiting state in which there is no exchange of message between the vehicle controller and the rewriting device. The rewriting device is in a waiting state until a predetermined waiting time has elapsed from the time at which a signal for requesting the vehicle controller to delete the data or write the new data is sent, or from the time at which a signal indicative of start of deleting operation of the data or writing operation of the new data is received. Thus, an erroneous determination of offline due to a busy state of the vehicle controller caused by deleting or writing operation is avoided.

Abstract: At least one transistor (MPX) is connected between a plurality of word line driving element circuits formed by using CMOS inverters (MP0 and MN0, etc.) and a source potential (Vcc). This transistor (MPX) is independently controlled by a control signal (DECENB) separate from control signals (AB-0 to AB-n) of the word line driving element circuits and has both a through current preventing function by adjusting timing and a peak current reducing function by limiting an electric current. Even when all word lines (SWL0 to SWLn) are driven at the same time, the electric current is limited and the peak current is suppressed.

Abstract: A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Abstract: A data mask section outputs memory data read from a memory array unit for a predetermined time period that is shifted from an edge timing of a clock signal, while a microcomputer takes in the data output from the data mask section at the edge timing of the clock signal. Thus, the microcomputer is capable of appropriately taking in the memory data only when the frequency of the clock signal is within a predetermined range, and accordingly, it is difficult to fraudulently obtain the memory data. Furthermore, the data mask section may output random data, or the like, during a time period other than the predetermined time period. In such a case, it is difficult to analyze the memory data, and the confidentiality of the memory data is improved.

Abstract: The semiconductor memory of this invention includes a memory cell, a control word line selector/deriver circuit, a well driver circuit, a source line selector/deriver circuit, a pulse generation circuit for outputting a pulse signal in injecting electrons into a floating gate of the memory cell, a first delay circuit, a second delay circuit and a third delay circuit. The control word line selector/deriver circuit changes the potential of a control word line in response to a first delay signal received from the first delay circuit, the well driver circuit changes the potential of a well in response to a second delay signal received from the second delay circuit, and the source line selector/deriver circuit changes the potential of a source line in response to a third delay signal received from the third delay circuit.

Abstract: The semiconductor memory of this invention includes a memory cell, a control word line selector/deriver circuit, a well driver circuit, a source line selector/deriver circuit, a pulse generation circuit for outputting a pulse signal in injecting electrons into a floating gate of the memory cell, a first delay circuit, a second delay circuit and a third delay circuit. The control word line selector/deriver circuit changes the potential of a control word line in response to a first delay signal received from the first delay circuit, the well driver circuit changes the potential of a well in response to a second delay signal received from the second delay circuit, and the source line selector/deriver circuit changes the potential of a source line in response to a third delay signal received from the third delay circuit.

Abstract: A vehicle controller comprises a first buffer for storing at least one data block, a second buffer for storing at least one data block, and a rewritable non-volatile memory for storing information for controlling a vehicle. The controller receives a data block from an external rewriting device to store it in the first buffer. The data block stored in the first buffer is transferred to the second buffer. The data block stored in the second buffer is written into the memory. When a first data block is written into the memory, a subsequent data block is received. Thus, the time required to rewrite data stored in the nonvolatile memory is reduced.

Abstract: A memory rewriting system for a vehicle controller is provided. The memory rewriting system transfers a first program from a rewriting device to the vehicle to rewrite a second program stored in a memory of the vehicle controller with the first program. The first program is transferred as data blocks. Each of the data blocks includes a program code field, a first address field and a second address field. The program code field contains a partial program code of the first program. The first address field contains a leading address of the memory in which the partial program code is stored. The second address field contains a leading address of the memory in which a following partial program code transferred by another block is to be stored. The data blocks are assembled in the rewriting device. Each data block is may be a fixed length or a variable length.

Abstract: An electrical connector comprises an insulative housing (1) of a rectangular paralellepiped, a plurality of contact elements (2) installed on both sides of the housing, a pair of shield plates (7) provided on longitudinal sides of the housing and a pair of reinforcing plates (15) provided on ends of the housing and each having a fixing leg, wherein ends of the reinforcing plate contact ends of the shield plate. The shield plate is positioned within the length of the housing, and the reinforcing plates comprises a main part provided at the ends of the housing and an auxiliary parts bent in parallel with the side surfaces of the shield plates, wherein the auxiliary parts overlap the ends of the shield plate to make spring contact with the shield plate.

Abstract: The rewriting system for rewriting data stored in a memory of a vehicle controller with new data is provided. The rewriting device is capable of communicating with the vehicle controller. The rewriting device enters a waiting state in which there is no exchange of message between the vehicle controller and the rewriting device. The rewriting device is in a waiting state until a predetermined waiting time has elapsed from the time at which a signal for requesting the vehicle controller to delete the data or write the new data is sent, or from the time at which a signal indicative of start of deleting operation of the data or writing operation of the new data is received. Thus, an erroneous determination of offline due to a busy state of the vehicle controller caused by deleting or writing operation is avoided.

Abstract: The rewriting device for rewriting data stored in a memory of a vehicle controller with new data is provided. The rewriting device is capable of communicating with the vehicle controller. When deleting or writing operation on the memory is not being performed, the rewriting device determines that communication between the rewriting device and the vehicle controller is offline if no response from the vehicle controller within a first determination time. When deleting operation or writing operation on the memory is being performed, the determination of offline is prohibited until a second determination time has elapsed. The second determination time is greater than the first determination time. It is preferable that the second determination time for deleting operation is the time necessary to delete the data stored in the memory, and that the second determination time for writing operation is the time necessary to write the new data into the memory.