Patents by Inventor Masanori Onodera

Masanori Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018105
    Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 25, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Publication number: 20200058610
    Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 20, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 10347618
    Abstract: Various embodiments of the present disclosure include a non-volatile memory semiconductor device and a device that uses the same, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present disclosure, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 9, 2019
    Assignee: VALLEY DEVICE MANAGEMENT
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
  • Patent number: 10200642
    Abstract: A camera module of the disclosure includes: an imaging unit that includes a plurality of pixels, acquires a first detection value in one of the pixels in a second term out of a first term, the second term, a third term, and a fourth term that are set in order, acquires a second detection value in the relevant one of the pixels in the fourth term, and obtains a pixel value of the relevant one of the pixels on the basis of a difference between the first and second detection values; a lens unit including a lens and an actuator that drives the lens; and a driver unit that generates a drive signal and drives the actuator using the drive signal, in which the drive signal makes a transition in each of the first and third terms.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 5, 2019
    Assignees: SONY CORPORATION, ROHM CO., LTD.
    Inventors: Takahiro Akahane, Ken Koseki, Kenichi Shigenami, Go Asayama, Rei Takamori, Tatsuya Ninomiya, Masato Nishinouchi, Masanori Onodera, Tatsuro Shimizu
  • Publication number: 20180220088
    Abstract: A camera module of the disclosure includes: an imaging unit that includes a plurality of pixels, acquires a first detection value in one of the pixels in a second term out of a first term, the second term, a third term, and a fourth term that are set in order, acquires a second detection value in the relevant one of the pixels in the fourth term, and obtains a pixel value of the relevant one of the pixels on the basis of a difference between the first and second detection values; a lens unit including a lens and an actuator that drives the lens; and a driver unit that generates a drive signal and drives the actuator using the drive signal, in which the drive signal makes a transition in each of the first and third terms.
    Type: Application
    Filed: March 1, 2016
    Publication date: August 2, 2018
    Inventors: TAKAHIRO AKAHANE, KEN KOSEKI, KENICHI SHIGENAMI, GO ASAYAMA, REI TAKAMORI, TATSUYA NINOMIYA, MASATO NISHINOUCHI, MASANORI ONODERA, TATSURO SHIMIZU
  • Publication number: 20180076188
    Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.
    Type: Application
    Filed: November 21, 2017
    Publication date: March 15, 2018
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
  • Patent number: 9887178
    Abstract: An example method includes disposing a semiconductor element on a first surface of a substrate. The substrate includes multiple solder balls mounted on a second surface of the substrate that is opposite to the first surface. The semiconductor element includes a bottom surface adjacent to the first surface of the substrate, a top surface, and multiple side surfaces. The example method includes forming a first molding portion to entirely enclose the multiple side surfaces and the top surface of the semiconductor element. The example method includes removing a second molding portion from the first molding portion to expose all of the top surface of the semiconductor element, leaving a third molding portion entirely enclosing the multiple sides surfaces of the semiconductor element, and coupling the semiconductor element to the first surface of the substrate by forming electrical connection between the semiconductor element and a first of the multiple solder balls.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: February 6, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventor: Masanori Onodera
  • Patent number: 9837397
    Abstract: Various embodiments of the present disclosure include a non-volatile memory semiconductor device and a device that uses the same, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present disclosure, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 5, 2017
    Assignee: VALLEY DEVICE MANAGEMENT
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
  • Publication number: 20170092606
    Abstract: A semiconductor device includes a semiconductor chip, a bump contact, and encapsulating layer, an insulating layer and a connection terminal.
    Type: Application
    Filed: October 28, 2016
    Publication date: March 30, 2017
    Inventors: Masanori Onodera, Junichi Kasai
  • Publication number: 20170069614
    Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.
    Type: Application
    Filed: October 13, 2016
    Publication date: March 9, 2017
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
  • Patent number: 9508651
    Abstract: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 9472540
    Abstract: Various embodiments of the present invention include a method for making a semiconductor device the method including disposing a first semiconductor chip on a first surface of a first substrate, the first substrate comprising a second surface opposing the first surface, depositing a first resin above the first semiconductor chip, disposing a built-in semiconductor device on the first resin. The built-in semiconductor device including a second substrate, a second semiconductor chip disposed on the second substrate, and a second resin that seals the second semiconductor chip. The method including depositing a third resin above the built-in semiconductor device and the first resin and covering a side surface of the first substrate and not extending beyond the second surface of the first substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device fabrication method, in which downsizing and cost reduction can be realized.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 18, 2016
    Assignee: VALLEY DEVICE MANAGEMENT
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
  • Patent number: 9418940
    Abstract: Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: August 16, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masataka Hoshino, Masahiko Harayama, Koji Taya, Naomi Masuda, Masanori Onodera, Ryota Fukuyama
  • Publication number: 20160204081
    Abstract: The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 14, 2016
    Inventor: Masanori Onodera
  • Patent number: 9368424
    Abstract: A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to the electrode terminals. This makes it possible to prevent the occurrence of resin burrs on the interposer and contamination of the electrode pads and to improve the production yield.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: June 14, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yasuhiro Shinma, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Junji Tanaka
  • Patent number: 9312252
    Abstract: A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10 is mounted; a first molding resin 14 that is provided on the upper surface of the first interposer 12 and seals the first semiconductor package 10; a second semiconductor package 20 mounted on an upper surface of the first molding resin 14; a second interposer 22 on which the second semiconductor package 20 is mounted by flip chip bonding; and a second molding resin 40 that is provided on the upper surface of the first interposer 12 and seals the first molding resin 14, the second semiconductor package 20, and the second interposer 22. The second semiconductor package 20 is mounted, with a surface thereof opposite to another surface mounted on the second interposer 22 faced down, on the upper surface of the first molding resin 14 via an adhesive 30.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 12, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Masanori Onodera
  • Patent number: 9293441
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: March 22, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Patent number: 9245774
    Abstract: The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 26, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Masanori Onodera
  • Patent number: 9142440
    Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 22, 2015
    Assignee: Cypess Semiconductor Corporation
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Publication number: 20150255446
    Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 10, 2015
    Inventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka