Patents by Inventor Masanori Shirahama
Masanori Shirahama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150078061Abstract: A semiconductor memory device includes a non-volatile device array of once rewritable non-volatile devices arranged in a matrix. The device includes a plurality of non-volatile device sub-arrays formed by dividing the non-volatile device array; a power interconnect contact region provided between at least one of pairs of the plurality of non-volatile device sub-arrays, and connected to a power interconnect provided at an upper layer of the non-volatile device array; and an ESD protection circuit located in the power interconnect contact region between ground and a power source for the non-volatile devices.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Inventors: Masanori SHIRAHAMA, Toshiaki KAWASAKI, Kazuhiro TAKEMURA, Yasuhiro AGATA
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Publication number: 20150036411Abstract: A semiconductor memory device includes a nonvolatile device array including write-once nonvolatile devices arranged in rows and columns, row select lines, a row control circuit connected to the row select lines, column select lines, a column control circuit connected to the column select lines, a flip-flop circuit provided at least on a side of the nonvolatile device array opposite to the row control circuit or on a side of the nonvolatile device array opposite to the column control circuit, and an inactivation unit configured to inactivate the row select lines or the column select lines based on a first control signal.Type: ApplicationFiled: October 16, 2014Publication date: February 5, 2015Inventors: Masanori SHIRAHAMA, Toshiaki KAWASAKI, Kazuhiro TAKEMURA, Yasuhiro AGATA
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Patent number: 8384466Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.Type: GrantFiled: March 12, 2012Date of Patent: February 26, 2013Assignee: Panasonic CorporationInventors: Toshiaki Kawasaki, Yasuhiro Agata, Masanori Shirahama, Toshihiro Kougami, Katsuya Arai
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Publication number: 20120169402Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: PANASONIC CORPORATIONInventors: TOSHIAKI KAWASAKI, YASUHIRO AGATA, MASANORI SHIRAHAMA, TOSHIHIRO KOUGAMI, KATSUYA ARAI
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Publication number: 20120146156Abstract: A semiconductor device includes an MIS transistor and an electric fuse. The MIS transistor includes a gate insulating film formed on the semiconductor substrate, and a gate electrode including a first polysilicon layer, a first silicide layer, and a first metal containing layer made of a metal or a conductive metallic compound. The electric fuse includes an insulating film formed on the semiconductor substrate, a second polysilicon layer formed over the insulating film, and a second silicide layer formed on the second polysilicon layer.Type: ApplicationFiled: February 15, 2012Publication date: June 14, 2012Applicant: PANASONIC CORPORATIONInventors: MASANORI SHIRAHAMA, YASUHIRO AGATA, TOSHIAKI KAWASAKI, YUICHI HIROFUJI, TAKAYUKI YAMADA
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Patent number: 8094498Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: GrantFiled: June 2, 2010Date of Patent: January 10, 2012Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki
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Patent number: 8072823Abstract: A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.Type: GrantFiled: October 22, 2010Date of Patent: December 6, 2011Assignee: Panasonic CorporationInventors: Tomoyuki Aihara, Masanori Shirahama, Yoshinobu Yamagami, Marefusa Kurumada, Toshikazu Suzuki
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Patent number: 8072832Abstract: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.Type: GrantFiled: September 22, 2010Date of Patent: December 6, 2011Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Yutaka Terada, Kenji Misumi, Masanori Shirahama, Mitsuaki Hayashi
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Publication number: 20110141825Abstract: A semiconductor integrated circuit system comprises a semiconductor memory device including a memory cell array having a plurality of memory cells; a monitor circuit for monitoring characteristics of the memory cells; and a voltage output circuit connected to the semiconductor memory device to supply a power supply voltage to the semiconductor memory device; the voltage output circuit being configured to change an output voltage according to an output of the monitor circuit.Type: ApplicationFiled: February 28, 2011Publication date: June 16, 2011Applicant: PANASONIC CORPORATIONInventors: Ichiro Hatanaka, Kenji Misumi, Tomoyuki Aihara, Masanori Shirahama
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Publication number: 20110032779Abstract: A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.Type: ApplicationFiled: October 22, 2010Publication date: February 10, 2011Applicant: Panasonic CorporationInventors: Tomoyuki AIHARA, Masanori SHIRAHAMA, Yoshinobu YAMAGAMI, Marefusa KURUMADA, Toshikazu SUZUKI
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Patent number: 7884642Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: GrantFiled: March 11, 2010Date of Patent: February 8, 2011Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Publication number: 20110007595Abstract: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.Type: ApplicationFiled: September 22, 2010Publication date: January 13, 2011Applicant: PANASONIC CORPORATIONInventors: Yasuhiro AGATA, Yutaka Terada, Kenji Misumi, Masanori Shirahama, Mitsuaki Hayashi
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Publication number: 20100238735Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: ApplicationFiled: June 2, 2010Publication date: September 23, 2010Applicant: Panasonic CorporationInventors: Yasue YAMAMOTO, Masanori SHIRAHAMA, Yasuhiro AGATA, Toshiaki KAWASAKI
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Patent number: 7791973Abstract: A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.Type: GrantFiled: January 29, 2008Date of Patent: September 7, 2010Assignee: Panasonic CorporationInventors: Shinichi Sumi, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara
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Patent number: 7764108Abstract: A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.Type: GrantFiled: October 26, 2007Date of Patent: July 27, 2010Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Shinichi Sumi, Yasue Yamamoto
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Patent number: 7755941Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: GrantFiled: January 9, 2008Date of Patent: July 13, 2010Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki
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Publication number: 20100164542Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: ApplicationFiled: March 11, 2010Publication date: July 1, 2010Applicant: Panasonic CorporationInventors: Yasuhiro AGATA, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7696779Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: GrantFiled: September 26, 2006Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7623380Abstract: A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.Type: GrantFiled: September 25, 2006Date of Patent: November 24, 2009Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki
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Patent number: 7602231Abstract: A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.Type: GrantFiled: September 25, 2006Date of Patent: October 13, 2009Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki