Patents by Inventor Masao Hotta
Masao Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8994572Abstract: The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing.Type: GrantFiled: September 6, 2012Date of Patent: March 31, 2015Assignee: Japan Science and Technology AgencyInventors: Hao San, Tsubasa Maruyama, Masao Hotta
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Publication number: 20140300500Abstract: The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing.Type: ApplicationFiled: September 6, 2012Publication date: October 9, 2014Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Hao San, Tsubasa Maruyama, Masao Hotta
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Patent number: 8258992Abstract: A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at thType: GrantFiled: October 19, 2010Date of Patent: September 4, 2012Assignee: Semiconductor Technology Academic Research CenterInventors: Masao Hotta, Tatsuji Matsuura
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Patent number: 8107912Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: December 22, 2010Date of Patent: January 31, 2012Assignees: Renesas Electronics Corporation, Tipcom LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Publication number: 20110092175Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicants: RENESAS TECHNOLOGY CORP., TTPCOM LIMITEDInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Publication number: 20110090103Abstract: A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at thType: ApplicationFiled: October 19, 2010Publication date: April 21, 2011Applicant: Semiconductor Technology Academic Research CenterInventors: Masao Hotta, Tatsuji Matsuura
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Patent number: 7885626Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: March 27, 2008Date of Patent: February 8, 2011Assignees: Renesas Technology Corp., TTPCOM LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Patent number: 7561094Abstract: An analog-to-digital converter has a digital-to-analog converter, first, second and third comparators, and a sequential comparison register and control logic circuit. The digital-to-analog converter produces analog signals, the first, second and third comparators compare the input analog signal with first, second and third analog signals which are different from each other. Further, the sequential comparison register and control logic circuit controls the digital signals that are fed to the digital-to-analog converter from the first to third comparators, and outputs the digital signals as digital values obtained by subjecting the input analog signals to the analog-to-digital conversion.Type: GrantFiled: August 15, 2007Date of Patent: July 14, 2009Assignee: Semiconductor Technology Academic Research CenterInventors: Masao Hotta, Tatsuji Matsuura
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Publication number: 20080182538Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: March 27, 2008Publication date: July 31, 2008Inventors: Satoshi TANAKA, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Publication number: 20080106453Abstract: An analog-to-digital converter has a digital-to-analog converter, first, second and third comparators, and a sequential comparison register and control logic circuit. The digital-to-analog converter produces analog signals, the first, second and third comparators compare the input analog signal with first, second and third analog signals which are different from each other. Further, the sequential comparison register and control logic circuit controls the digital signals that are fed to the digital-to-analog converter from the first to third comparators, and outputs the digital signals as digital values obtained by subjecting the input analog signals to the analog-to-digital conversion.Type: ApplicationFiled: August 15, 2007Publication date: May 8, 2008Applicant: Semiconductor Technology Academic Research CenterInventors: Masao Hotta, Tatsuji Matsuura
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Patent number: 7366489Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: December 23, 2003Date of Patent: April 29, 2008Assignees: TTPCOM Limited, Renesas Technology Corp.Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Patent number: 6826388Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: GrantFiled: November 14, 2000Date of Patent: November 30, 2004Assignee: Renesas Technology Corp.Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Publication number: 20040137941Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicants: Renesas Technology Corp., TTPCom LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Publication number: 20040137853Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicants: Renesas Technology Corp., TTPCom LimitedInventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
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Patent number: 6492872Abstract: A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power amplifier module in a multi-stage configuration including a plurality of cascaded MOSFETS. The power amplifier module comprises a bias circuit for generating a gate voltage in response to a power control voltage (vapc) generated based on a power control signal of the wireless communication apparatus. The gate voltage has a bias pattern which presents smaller fluctuations in output power in response to a control voltage (Vapc) in a region near a threshold voltage (Vth) of the MOSFETs in respective amplification stages. In this way, the controllability for the output power is improved. More specifically, the power amplifier module has a gate bias circuit for generating the gate voltage (Vg) which follows a gate voltage pattern.Type: GrantFiled: September 7, 2000Date of Patent: December 10, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Toru Fujioka, Yoshikuni Matsunaga, Isao Yoshida, Masatoshi Morikawa, Masao Hotta, Tetsuaki Adachi
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Patent number: 6226605Abstract: Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation.Type: GrantFiled: August 11, 1998Date of Patent: May 1, 2001Assignee: Hitachi, Ltd.Inventors: Yoshito Nejime, Hiroshi Ikeda, Masao Hotta
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Patent number: 5966407Abstract: A bus driving system includes n bus wires having data signal wires and control signal wires, (n-1) switching circuits constituting driver circuits at a transmitting end, a precharge circuitry for precharging (n-2) bus wires and (n-1)-th bus wire with a control circuit for redistributing wire capacitances of transmission lines formed by the bus wires, and a predischarge circuitry for predischarging n-th bus wire. The switching circuits control conduction and non-conduction between (n-2) bus wires, (n-1)-th bus wire and n-th bus wire, wherein the (n-2) switching circuits respond to (n-2) bit signals and a control signal, while the (n-1)-th switching circuit responds to the control signal. The signal from the transmitting end is detected by a detection circuit at a receiving end via the transmission lines.Type: GrantFiled: May 31, 1994Date of Patent: October 12, 1999Assignee: Hitachi, Ltd.Inventors: Mitsuru Hiraki, Hirotsugu Kojima, Masaru Kokubo, Takafumi Kikuchi, Yuji Hatano, Kouki Noguchi, Masao Hotta
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Patent number: 5794201Abstract: Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation.Type: GrantFiled: June 5, 1995Date of Patent: August 11, 1998Assignee: Hitachi, Ltd.Inventors: Yoshito Nejime, Hiroshi Ikeda, Masao Hotta
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Patent number: 5623533Abstract: In a mobile wireless communication end device having an electric power source including a cell, and a signal processing part and a transmitting-receiving part, to which electric power is applied from the electric power source, operation is performed in operation mode selected previously by the user when voltage of the electric power source is dropped. The signal processing part and the transmitting-receiving part have a normal operation mode operating at normal electric power and a low power operation mode operating at electric power lower than the normal operation mode.Type: GrantFiled: March 26, 1996Date of Patent: April 22, 1997Assignee: Hitachi, Ltd.Inventors: Takafumi Kikuchi, Yuji Hatano, Koichi Seki, Masanori Otsuka, Masao Hotta, Yasuyuki Murakami
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Patent number: 5519398Abstract: A signal processing apparatus for converting an analog signal to a digital signal and processing the digital signal. In particular, a digital filter for performing processing at high speed is implemented by using an integrated circuit of low power consumption. The signal processing apparatus includes a circuit for comparing an input analog signal with each voltage of a plurality of analog reference voltages and generating a thermometer code Tc depending upon the analog input signal, a decoder for detecting a change point of the thermometer code Tc, and a plurality of memory circuits having output signal lines of the decoder as word selection lines. The product of an input signal value corresponding to each word selection line and a predetermined filter coefficient is stored in the corresponding word of the memory circuits. The memories are used as look-up tables.Type: GrantFiled: October 13, 1993Date of Patent: May 21, 1996Assignee: Hitachi, Ltd.Inventors: Naoki Satoh, Hirotsugu Kojima, Hideki Sawaguchi, Masao Hotta