Patents by Inventor Masao Suga

Masao Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010021956
    Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 13, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kosei Okamoto, Hiroyuki Sakamoto, Akihisa Fujimoto, Masao Suga
  • Patent number: 5537531
    Abstract: A portable computer that includes a first ROM for storing an OS, a second ROM for storing at least one piece of existing application software, and a flat display panel for displaying at least one icon to read out the existing application software stored in the second ROM. Since the DOS and the application program are respectively stored in a DOS ROM and an application ROM, the DOS or the application can be quickly executed without install processing from floppy disks.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: July 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Suga, Syuzo Nakajima, Tadaaki Inomata, Toshimitsu Saito, Atsuhiro Outake, Yoshiaki Iba, Hidekazu Mihara, Hirofumi Nishikawa, Nobuyuki Nanno, Shigeru Satake
  • Patent number: 5497455
    Abstract: When the MS-DOS is not installed from an FDD or an HDD but is installed from a built-in DOS ROM arranged in a memory space in which bank access to the computer main body can be performed, at the time the system power is turned on, a menu display processing program stored in the DOS ROM is executed by the DOS. Upon execution of the program, the arrangement of menu icons can be arbitrarily changed on the menu screen.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: March 5, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Suga, Syuzo Nakajima, Tadaaki Inomata, Toshimitsu Saito, Atsuhiro Outake, Yoshiaki Iba, Hidekazu Mihara, Hirofumi Nishikawa, Nobuyuki Nanno, Shigeru Satake
  • Patent number: 4807119
    Abstract: A memory address mapping mechanism includes a flip-flop for latching a signal (PROT) representing the real or protective virtual address mode. AN output signal from the flip-flop is supplied to an address decoder. In either the real or protective virtual address mode, the address decoder receives the address signal from a microprocessor and the signal (PROT) from the flip-flop, decodes the address signal so as to obtain a continuous memory address space, and outputs a memory address selection signal.
    Type: Grant
    Filed: July 24, 1986
    Date of Patent: February 21, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masao Suga
  • Patent number: 4457819
    Abstract: The present invention provides a method of delustering an electrocoated article which comprises dipping an uncured electrocoated article into an aqueous solution of an organic sulfonic acid, and applying electric voltage to the article. Further, the present invention provides a method of controlling the gloss of an electrocoated article which comprises electrocoating an article while applying pulsating electric current voltage, dipping the obtained electrocoated article in an aqueous solution of an organic sulfonic acid in an uncured state, and applying electric voltage to the electrocoated article as anode, wherein certain pulsating ratio at electrocoating is selected. According to the present invention, an even delustered coat having excellent physical properties is obtained. Further, it is possible to deluster the electrocoat to a desirable gloss with eveness.
    Type: Grant
    Filed: December 28, 1982
    Date of Patent: July 3, 1984
    Assignees: Nippon Paint Co., Ltd., Nippon Light Metal Company Ltd.
    Inventors: Hisao Kirino, Yukinobu Yabumoto, Takashi Iritani, Masao Suga, Yukinaga Nakanishi, Masaru Itoh