Patents by Inventor Masao Takahashi
Masao Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8367210Abstract: The invention provides the advantages of a metallic housing and those of a synthetic resin structure for electronic devices, home electrical devices, etc., achieves high productivity and mass productivity, and enables a desired configuration and structure to be designed freely. As a pretreatment, a shaped aluminum alloy material is dipped in an aqueous solution of at least one selected from the group consisting of ammonia, hydrazine, and a water-soluble amine compound. A thermoplastic resin composition containing polyphenylene sulfide as a component is integrally bonded to the surface of the treated shaped aluminum alloy material by injection molding or other method. The molded article is a product made of the shaped aluminum alloy material and the thermoplastic resin composition containing PPS. Thus, the characteristic features of metal can be utilized in terms of mechanical strength and external appearance design. Moreover, a complicated configuration and structure can be formed inside the housing.Type: GrantFiled: November 7, 2003Date of Patent: February 5, 2013Assignee: Taisei Plas Co., Ltd.Inventors: Masanori Naritomi, Naoki Ando, Masao Takahashi
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Patent number: 8338829Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: GrantFiled: July 8, 2011Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
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Patent number: 8334509Abstract: A particle beam irradiation apparatus includes a beam scanning indication unit which two-dimensionally indicates a position of a particle beam in series for each of slices obtained by dividing an affected area to be irradiated in an axial direction of the particle beam, a beam scanning unit which two-dimensionally scans the particle beam based on an indication signal from the beam scanning indication unit, a phosphor film which is provided between the beam scanning unit and a patient and emits light in an amount corresponding to a particle dose of the particle beam transmitting therethrough, an imaging unit which images the phosphor film for each of the slices, and a display unit which obtains an irradiation dose distribution of each of the slices from image data imaged by the imaging unit and displays the obtained irradiation dose distribution associated with a scanning position of the particle beam.Type: GrantFiled: August 20, 2010Date of Patent: December 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Iseki, Masao Takahashi, Katsushi Hanawa, Kazunao Maeda, Atsuo Inoue, Teruyasu Nagafuchi, Nobukazu Kakutani
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Patent number: 8319958Abstract: The present invention provides a photosensor that uses a phase modulation technique for optical detection and conducts a highly accurate measurement. The photosensor uses a phase change difference of light propagated through a polarization preserving fiber with respect to tensile stress and employs proper polarization preserving fibers for a phase modulator 10, light-transmitting polarization preserving fiber 23, and coil-shaped polarization preserving fiber 30, to achieve a highly accurate measurement.Type: GrantFiled: January 9, 2009Date of Patent: November 27, 2012Assignees: Kabushiki Kaisha Toshiba, Toshiba Industrial Products Manufacturing CorporationInventors: Kinichi Sasaki, Masao Takahashi, Masahiro Hamaguchi, Takashi Miyabe, Tsuyoshi Kuwabara, Tokihiro Umemura
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Patent number: 8304856Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.Type: GrantFiled: September 13, 2010Date of Patent: November 6, 2012Assignees: Sanyo Semiconductor Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Keiji Mita, Yasuhiro Tamada, Masao Takahashi, Takao Maruyama
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Patent number: 8237281Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: January 4, 2011Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Patent number: 8232623Abstract: A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.Type: GrantFiled: December 12, 2008Date of Patent: July 31, 2012Inventors: Keiji Mita, Masao Takahashi, Takao Arai
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Publication number: 20120080780Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8115473Abstract: An optical voltage transformer is connected with an external electric device and includes a primary electrode to which a measured voltage is applied by the external electric device, a first secondary electrode provided oppositely to the primary electrode, an insulation layer provided between the primary and first secondary electrodes and constituting an insulation cylinder integrally formed with the primary and first secondary electrodes, a ground layer provided on an outer circumference of the insulation cylinder and around the first secondary electrode for securing a capacitance by interposing the insulation layer between the ground layer and the first secondary electrode, and an electro-optic element for measuring a voltage between the first secondary electrode and the ground layer.Type: GrantFiled: April 7, 2008Date of Patent: February 14, 2012Assignees: Kabushiki Kaisha Toshiba, Toshiba Industrial Products Manufacturing CorporationInventors: Junichi Sato, Masao Takahashi, Miwa Takeuchi, Teruhiko Maeda, Mitsuhiro Fujikawa, Tokihiro Umemura, Tsuyoshi Kuwabara
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Patent number: 8102056Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: August 29, 2006Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Publication number: 20110266540Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: Panasonic CorporationInventors: Masao TAKAHASHI, Koji TAKEMURA, Toshihiko SAKASHITA, Tadaaki MIMURA
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Publication number: 20110234202Abstract: A polarizing optical system (15, 16) is disposed perpendicular to an optical axis of incoming light from a light source (12), having the optical axis (12) as a center axis, and configured for polarization of incoming light to a prescribed reference state, an electro-optical device (17) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted, as a voltage to be measured is imposed thereon, to respond to the imposed voltage by polarizing light polarized by the polarizing optical system (15, 16), and an analyzer (18) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted for detection of light polarized by the electro-optical device (17), to irradiate a detector (21) configured for conversion of incoming light into an electric signal.Type: ApplicationFiled: May 27, 2009Publication date: September 29, 2011Inventors: Masao Takahashi, Junichi Sato, Takashi Miyabe, Tokihiro Umemura, Tsuyoshi Kuwabara
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Patent number: 7999256Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: GrantFiled: September 11, 2008Date of Patent: August 16, 2011Assignee: Panasonic CorporationInventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
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Publication number: 20110141478Abstract: In one embodiment, a Sagnac interferometer-type fiber-optic sensor includes a synchronous detection circuit to carry out synchronous detection of detected light signal with a phase modulation angular frequency of a phase modulator. A signal processing circuit calculates and outputs the magnitude of current to be measured using the signal detected in the synchronous detection circuit. A phase modulator driving circuit controls the driving of the phase modulator. The phase modulator driving circuit controls a phase modulation depth of the phase modulator so that the amplitude of the second-order harmonics and the fourth-order harmonics obtained by carrying out the synchronous detection of the detected light signal with the phase modulation angular frequency becomes the same.Type: ApplicationFiled: December 10, 2010Publication date: June 16, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kinichi SASAKI, Masao Takahashi, Yukihisa Hirata
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Publication number: 20110095430Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20110079880Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.Type: ApplicationFiled: September 13, 2010Publication date: April 7, 2011Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Keiji Mita, Yasuhiro Tamada, Masao Takahashi, Takao Maruyama
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Publication number: 20110049372Abstract: The particle beam irradiation apparatus according to the present invention comprises: a beam generation unit; a beam emission control unit which controls emission of the particle beam; a beam scanning indication unit which two-dimensionally indicates a position of the particle beam in series for each of slices obtained by dividing an affected area to be irradiated in an axial direction of the particle beam; a beam scanning unit which two-dimensionally scans the particle beam based on an indication signal from the beam scanning indication unit; a phosphor film which is provided between the beam scanning unit and a patient and emits light in an amount corresponding to a particle dose of the particle beam transmitting therethrough; an imaging unit which images the phosphor film for each slice; and a display unit which obtains an irradiation dose distribution of each slice from image data imaged by the imaging unit and displays the obtained irradiation dose distribution associated with a scanning position of theType: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yasushi ISEKI, Masao TAKAHASHI, Katsushi HANAWA, Kazunao MAEDA, Atsuo INOUE, Teruyasu NAGAFUCHI, Nobukazu KAKUTANI
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Patent number: 7888801Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: April 27, 2009Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20110002563Abstract: A sliding bearing 5 is composed of a pair of halved bearings 11, 12 and is provided with crush reliefs 11E, 12E in positions adjoining abutment surfaces 11B, 12B of these halved bearings. Chamfered portions 11D, 12D are formed in inward edge portions of the above-described abutment surfaces 11B, 12B, and a dust pocket 15 is formed on the middle side of the chamfered portions 11D, 12D. The relative angle ? formed by the above-described crush reliefs 11E, 12E with sliding surfaces 13 in positions adjoining the crush reliefs 11E, 12E is set at 0.69° or more. Foreign substances 14 in a lubricating oil are discharged from openings of side portions of the crush reliefs 11E, 12E to the outside and are prevented from easily entering the sliding surfaces 13. A sliding bearing excellent in seizure resistance compared to that of conventional art can be provided.Type: ApplicationFiled: April 17, 2009Publication date: January 6, 2011Inventors: Yukiyasu Taguchi, Masaru Kondo, Takashi Tomikawa, Katsuhiro Ashihara, Masao Takahashi
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Publication number: 20100315621Abstract: The present invention provides a photosensor that uses a phase modulation technique for optical detection and conducts a highly accurate measurement. The photosensor uses a phase change difference of light propagated through a polarization preserving fiber with respect to tensile stress and employs proper polarization preserving fibers for a phase modulator 10, light-transmitting polarization preserving fiber 23, and coil-shaped polarization preserving fiber 30, to achieve a highly accurate measurement.Type: ApplicationFiled: January 9, 2009Publication date: December 16, 2010Inventors: Kinichi Sasaki, Masao Takahashi, Masahiro Hamaguchi, Takashi Miyabe, Tsuyoshi Kuwabara, Tokihiro Umemura