Abstract: An engine room temperature rise restricting apparatus including an open and close detector of the grille shutter, and a controller including a CPU and a memory coupled to the CPU, wherein the CPU and the memory are configured to perform: detecting a stuck-closed failure of a grille shutter of a condition that the grille shutter remains closed regardless of an open instruction for the grille shutter, based on signal from the open and close detector; and controlling a speed ratio of a continuously variable transmission so that an upper limit of an engine rotational speed or an engine driving force when the stuck-closed failure is detected is smaller than an upper limit of the engine rotational speed or the engine driving force when the stuck-closed failure is not detected.

Abstract: An engine room temperature rise restricting apparatus including an open and close detector of the grille shutter, and a controller including a CPU and a memory coupled to the CPU, wherein the CPU and the memory are configured to perform: detecting a stuck-closed failure of a grille shutter of a condition that the grille shutter remains closed regardless of an open instruction for the grille shutter, based on signal from the open and close detector; and controlling a speed ratio of a continuously variable transmission so that an upper limit of an engine rotational speed or an engine driving force when the stuck-closed failure is detected is smaller than an upper limit of the engine rotational speed or the engine driving force when the stuck-closed failure is not detected.

Abstract: Even when a surface temperature of an illumination optical system becomes high, detection accuracy of a reticle alignment detection system is not negatively affected. An illumination optical system irradiates an illumination light to a mask and exposes a substrate with the illumination light through the mask. A gas supply device supplies gas, which has been cleaned, to a case in which is disposed at least part of an illumination optical system. A temperature adjusting device adjusts the temperature of the case and the temperature in the vicinity of the case.

Abstract: A semiconductor memory device includes a data line for receiving a voltage and an inverted data line having a voltage inverted relative to the voltage received by the data line; a first transistor and a second transistor for selecting a memory element for writing in data and reading out data through the data line and the inverted data line, respectively; two inverters, each inverter including a first p channel transistor and a first n channel transistor with the input and the output of the one inverter respectively connected to the output and the input of the other inverter and between either the source and the drain of the first transistor or the drain and the source of the second transistor; and a second p channel transistor connected in series to the first p channel transistor of one of the two inverters.

Abstract: In order to obtain an output circuit having pulldown resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an OR gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pulldown transistor (Q.sub.1) are connected to a second input end and an output end of the OR gate (G5) respectively. The pulldown transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.SS) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a high logical level, the pulldown transistor (Q.sub.

Abstract: In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q.sub.1) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.DD) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a low logical level, the pullup transistor (Q.sub.

Abstract: A surge protection apparatus, has a signal terminal, and first and second power supply terminals which are connected to the internal circuit to be protected, and first and second diodes which are connected between the signal terminal and the first and second power supply terminals, and a protective transistor acting as a discharge path for the surge voltage which is connected between the first and the second power supply terminals. As a result, even if the discharge capability of the internal circuit connected between the first and second power supply terminals is small, the surge voltage can be discharged in a short time through the protective transistor. Moreover, since the protective diode at the positive power supply side is connected to the power source of low impedance, the plural signal terminals will not be coupled by the junction capacitance. Thus, crosstalk does not occur between the plural signal terminals.