Patents by Inventor Masao Tokunari

Masao Tokunari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914204
    Abstract: An optical connector device is provided. The optical connector device includes a semiconductor package including a receptacle and a lid. The optical connector device also included an adapter attached to the lid of the semiconductor package, and a connector removably attached to the adapter. The adapter includes a convex part adapted to fit into an adapter opening of the lid, an adapter recess adapted to accommodate at least a portion of the connector, and a first retainer in the adapter recess to removably attach the connector to the adapter at a predetermined position. The connector includes an optical fiber array corresponding to the receptacle and extending in a vertical direction with respect to a plane of the semiconductor package, a second retainer used in conjunction with the first retainer, and a biasing member to bias a portion of the connector toward the semiconductor package.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: February 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Masao Tokunari, Koji Masuda, Hsiang Han Hsu
  • Publication number: 20230204861
    Abstract: Techniques for creating an SiGe/Si electro-optomechanical quantum transducer, comprising an SiGe/Si optical ring resonator and capacitor, that can be associated with a qubit are presented. The optical resonator, comprising an SiGe optical waveguide and a strained silicon membrane, can be formed and disposed over a substrate. The strained silicon membrane can have a photoelastic coupling with the SiGe optical waveguide. A capacitor, comprising a superconducting material, can be formed in proximity to the optical resonator. The top plate of the capacitor can be associated with the strained silicon membrane. A recessed region can be formed in the back side of the substrate along a desired silicon plane, extending to form a hole in the top side of the substrate. A superconducting material can be applied along substrate surfaces defining the recessed region and hole. The superconducting material covering the hole can be the bottom plate of the capacitor.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Inventors: Masao Tokunari, Ryan Daniel Schilling
  • Publication number: 20230180630
    Abstract: A vertical transmon qubit structure, includes a substrate having a first surface and a second surface. A through-silicon-via (TSV) is located in the substrate. A first electrode of a Josephson junction (JJ) is located on a portion of the first surface of the substrate and adjacent to the TSV. A second electrode of the JJ is in contact with the TSV and on a second portion of the first surface of the substrate. The first electrode is separated from the second electrode by an insulator.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Masao Tokunari, Naoki Kanazawa, Akihiro Horibe, Kuniaki Sueoka
  • Patent number: 11460647
    Abstract: A chip packaging structure that includes an optoelectronic (OE) chip mounted on a first surface of a substrate and whose optically active area is directed laterally; and a lens array for the optoelectronic (OE) chip that is mounted on the first surface of the substrate and faces to the optoelectronic (OE) chip, wherein the lens array has inside a reflector reflecting light from a first direction to a second direction, in which the first direction is substantially perpendicular to the second direction.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jean Benoit Heroux, Masao Tokunari
  • Publication number: 20220107478
    Abstract: An optical connector device is provided. The optical connector device includes a semiconductor package including a receptacle and a lid. The optical connector device also included an adapter attached to the lid of the semiconductor package, and a connector removably attached to the adapter. The adapter includes a convex part adapted to fit into an adapter opening of the lid, an adapter recess adapted to accommodate at least a portion of the connector, and a first retainer in the adapter recess to removably attach the connector to the adapter at a predetermined position. The connector includes an optical fiber array corresponding to the receptacle and extending in a vertical direction with respect to a plane of the semiconductor package, a second retainer used in conjunction with the first retainer, and a biasing member to bias a portion of the connector toward the semiconductor package.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 7, 2022
    Inventors: MASAO TOKUNARI, Koji Masuda, Hsiang Han Hsu
  • Patent number: 11181704
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 11112570
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Publication number: 20210116652
    Abstract: A chip packaging structure that includes an optoelectronic (OE) chip mounted on a first surface of a substrate and whose optically active area is directed laterally; and a lens array for the optoelectronic (OE) chip that is mounted on the first surface of the substrate and faces to the optoelectronic (OE) chip, wherein the lens array has inside a reflector reflecting light from a first direction to a second direction, in which the first direction is substantially perpendicular to the second direction.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventors: Jean Benoit Heroux, Masao Tokunari
  • Patent number: 10948659
    Abstract: Optoelectronic coupling systems include an optoelectronic chip mounted on a substrate. The optoelectronic chip has one or more optoelectronic components. An integrated circuit chip is mounted on the substrate in communication with the optoelectronic chip via one or more wires. A lower lens array is positioned over the optoelectronic chip. A lower surface of the lower lens array has a first cut-away portion to accommodate the optoelectronic chip and a second cut-away portion to accommodate the one or more wires. An upper surface of the lower lens array has one or more lower lenses positioned over respective optoelectronic components. An upper lens array is positioned over the lower lens array and has one or more upper lenses positioned over respective lower lenses.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hidetoshi Numata, Masao Tokunari
  • Patent number: 10914901
    Abstract: A chip packaging structure that includes an optoelectronic (OE) chip mounted on a first surface of a substrate and whose optically active area is directed laterally; and a lens array for the optoelectronic (OE) chip that is mounted on the first surface of the substrate and faces to the optoelectronic (OE) chip, wherein the lens array has inside a reflector reflecting light from a first direction to a second direction, in which the first direction is substantially perpendicular to the second direction.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Benoit Heroux, Masao Tokunari
  • Patent number: 10840428
    Abstract: Quantum computing devices include a chip carrier that has a conductive carrier body and one or more readout resonators in the conductive carrier body. Each readout resonator has a center conductor and a coaxial dielectric layer. A quantum chip is on the chip carrier and includes one or more qubits positioned over respective readout resonators.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Naoki Kanazawa, Masao Tokunari
  • Publication number: 20200319405
    Abstract: A method for forming an embedded mirror structure is disclosed. The method includes preparing a structure that has a substrate and a waveguide layer on the substrate. The waveguide layer includes a core. Also, the waveguide has a top surface and a cavity side surface that defines a cavity opened at the top surface and aligned to the core. The method further includes coating metal particles on the cavity side surface inside the cavity of the waveguide layer to form a metal particle film on the cavity side surface.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Hsiang Han Hsu, Masao Tokunari, Koji Masuda
  • Patent number: 10782480
    Abstract: An optoelectronic coupling system includes an optoelectronic chip mounted on a substrate, having one or more optoelectronic components. A lower lens array is positioned over the optoelectronic chip and has a lower surface with a first portion at a first height to mount on the substrate and a second portion at a second height, higher than the first height, to accommodate a height of the optoelectronic chip. The lower lens array has an upper surface that comprises one or more lower lenses positioned over respective optoelectronic components of the one or more optoelectronic components. An upper lens array is positioned over the lower lens array and has one or more upper lenses positioned over respective lower lenses.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hidetoshi Numata, Masao Tokunari
  • Patent number: 10775573
    Abstract: A method for forming an embedded mirror structure is disclosed. The method includes preparing a structure that has a substrate and a waveguide layer on the substrate. The waveguide layer includes a core. Also, the waveguide has a top surface and a cavity side surface that defines a cavity opened at the top surface and aligned to the core. The method further includes coating metal particles on the cavity side surface inside the cavity of the waveguide layer to form a metal particle film on the cavity side surface.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hsiang Han Hsu, Masao Tokunari, Koji Masuda
  • Publication number: 20200287117
    Abstract: Quantum computing devices include a chip carrier that has a conductive carrier body and one or more readout resonators in the conductive carrier body. Each readout resonator has a center conductor and a coaxial dielectric layer. A quantum chip is on the chip carrier and includes one or more qubits positioned over respective readout resonators.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Naoki Kanazawa, Masao Tokunari
  • Patent number: 10690867
    Abstract: An optical device includes a substrate including plural waveguide cores and an optical component provided on the substrate. The plural waveguide cores allowing light to pass through the plural waveguide cores and the optical component including plural lenses Each of the plural lenses transmitting light passing through a corresponding one of the plural waveguide cores on the substrate, wherein the optical component includes a body and a protrusion The body being provided with the plural lenses, the protrusion being protruded from a side of the body, and the protrusion is fixed to the substrate with an adhesive.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koji Masuda, Patrick Jacques, Paul Francis Fortier, Masao Tokunari
  • Patent number: 10656352
    Abstract: A micro-mirror array for optical coupling in a waveguide array including, a transparent body having a slanted portion, a sidewall portion, and a bottom portion, the sidewall portion and the bottom portion each respectively facing the slanted portion, and wherein a complementary shape of a conventional form off-axis mirror is arranged on the slanted portion, and a reflective coating on at least a portion of the complementary shape.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Benoit Héroux, Masao Tokunari
  • Publication number: 20200150362
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Publication number: 20200150361
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 10613282
    Abstract: An optical structure includes a substrate including a cavity on a first surface of the substrate, an optical component on the substrate and an adhesive applied to a side of the optical component to fix the optical component to the substrate. The optical component includes a recess on a second surface of the optical component, the second surface is opposed to the first surface of the substrate, and the recess is provided along an edge of the second surface.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Elaine Cyr, Paul F. Fortier, Takashi Hisada, Patrick Jacques, Koji Masuda, Masao Tokunari