Patents by Inventor Masaoki Kajiyama

Masaoki Kajiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7977767
    Abstract: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Yutaka Nabeshima, Masaoki Kajiyama, Tomohiro Matsunaga, Hidenori Iwadate
  • Publication number: 20090283855
    Abstract: An inductor having a helicoidal shape is provided on an insulation film formed on a semiconductor substrate. A conductive thin layer (a plating layer) is provided on a surface of the inductor. A conductivity of the conductive thin layer is higher than that of the inductor. According to the constitution, a Q value can be improved, and a large volume of current can be flowed.
    Type: Application
    Filed: May 18, 2009
    Publication date: November 19, 2009
    Inventors: Hidenori IWADATE, Masaoki KAJIYAMA
  • Publication number: 20090160018
    Abstract: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 25, 2009
    Inventors: Yutaka Nabeshima, Masaoki Kajiyama, Tomohiro Matsunaga, Hidenori Iwadate
  • Patent number: 5236851
    Abstract: A method for fabricating a bipolar or field effect-type integrated circuit transistor is provided in which non-crystalline semiconductor films and semiconductive regions formed in a single crystal semiconductor substrate and containing high concentrations of impurities are efficiently connected with improved electric characteristics while suppressing the influence of an increase in connection resistance caused by growth of a natural oxide film. Moreover, when a first non-crystalline semiconductor film is removed from a dielectric oxide film serving as a field film and a second non-crystalline semiconductor film is formed as a ribbon-shaped pattern on the exposed field film, a resistor of high accuracy can be formed. An interconnection system having resistors of a high accuracy and a fine size is also disclosed.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: August 17, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuichi Kameyama, Hiroyuki Sakai, Kazuya Kikuchi, Masaoki Kajiyama
  • Patent number: 5116770
    Abstract: A method for fabricating a bipolar or field effect-type integrated circuit transistor is provided in which non-cyrstalline semiconductor films and semiconductive regions formed in a single crystal semiconductor substrate and containing high concentrations of impurities are efficiently connected with improved electric characteristics while suppressing the influence of an increase in connection resistance caused by growth of a natural oxide film. Moreover, when a first non-crystalline semiconductor film is removed from a dielectric oxide film serving as a field film and a second non-crystalline semiconductor film is formed as a ribbon-shaped pattern on the exposed field film, a resistor of high accuracy can be formed. An interconnection system having resistors of a high accuracy and a fine size is also disclosed.
    Type: Grant
    Filed: July 12, 1989
    Date of Patent: May 26, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuichi Kameyama, Hiroyuki Sakai, Kazuya Kikuchi, Masaoki Kajiyama