Abstract: An image processing device includes an application execution unit which executes an image processing application, an image processing circuit which performs image processing, a memory control circuit which is capable of accessing a plurality of memories and a memory allocation determination unit which determines a memory allocation of the image data on the basis of memory address management information, operation unit-specific information and application information. The application execution unit distributedly stores the image data in the plurality of memories on the basis of the memory allocation determined by the memory allocation determination unit.

Abstract: An image processing device includes an application execution unit which executes an image processing application, an image processing circuit which performs image processing, a memory control circuit which is capable of accessing a plurality of memories and a memory allocation determination unit which determines a memory allocation of the image data on the basis of memory address management information, operation unit-specific information and application information. The application execution unit distributedly stores the image data in the plurality of memories on the basis of the memory allocation determined by the memory allocation determination unit.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a first register setting list and notifies the central processing unit of an access complete signal indicating completion of reading a second register setting list within a memory. The central processing unit changes the second register setting list within the memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the second register setting list changed by the central processing unit into the buffer to update the first register setting list based on the update request information.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a first register setting list and notifies the central processing unit of an access complete signal indicating completion of reading a second register setting list within a memory. The central processing unit changes the second register setting list within the memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the second register setting list changed by the central processing unit into the buffer to update the first register setting list based on the update request information.

Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a register setting list and notifies the central processing unit of an access complete signal indicating completion of reading the register setting list. The central processing unit changes the register setting list within a memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the register setting list changed by the central processing unit into the buffer based on the update request information.

Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section. and a. hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a register setting list and notifies the central processing unit of an access complete signal indicating completion of reading the register setting list. The central processing unit changes the register setting list within a memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the register setting list changed by the central processing unit into the buffer based on the update request information.

Abstract: A deaeration device for bubbling dissolved air in the cleaning liquid by cavitation is connected on a cleaning-liquid circulation path so as to bubble the dissolved air in the cleaning liquid flowing through the cleaning-liquid circulation path, and the bubbled dissolved air flows back to the cleaning tank together with the cleaning liquid so that the bubbled dissolved air is ejected from the liquid surface of the cleaning tank to the outside of the tank. Moreover, a propeller-type pump is used as the circulating pump, and the dissolved air concentration of the cleaning liquid is controlled within a range of 2.5 to 3.5 mg/l.

Abstract: The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.

Abstract: A deaeration device for bubbling dissolved air in the cleaning liquid by cavitation is connected on a cleaning-liquid circulation path so as to bubble the dissolved air in the cleaning liquid flowing through the cleaning-liquid circulation path by the deaeration device, and the bubbled dissolved air flows back to the cleaning tank together with the cleaning liquid so that the bubbled dissolved air is ejected from the liquid surface of the cleaning tank to the outside of the tank. Moreover, a propeller-type pump is used as the circulating pump, and the dissolved air concentration of the cleaning liquid is controlled within a range of 2.5 to 3.5 mg/l.

Abstract: A deaeration device for bubbling dissolved air in the cleaning liquid by cavitation is connected on a cleaning-liquid circulation path so as to bubble the dissolved air in the cleaning liquid flowing through the cleaning-liquid circulation path by the deaeration device, and the bubbled dissolved air flows back to the cleaning tank together with the cleaning liquid so that the bubbled dissolved air is ejected from the liquid surface of the cleaning tank to the outside of the tank. Moreover, a propeller-type pump is used as the circulating pump, and the dissolved air concentration of the cleaning liquid is controlled within a range of 2.5 to 3.5 mg/l.

Abstract: A cleaning-liquid circulation path is formed so that cleaning liquid in a cleaning tank is suctioned by a circulating pump and circulated through a predetermined path and then, returned to the cleaning tank again. A deaeration device for bubbling dissolved air in the cleaning liquid by cavitation is connected on the way of the cleaning-liquid circulation path so as to bubble the dissolved air in the cleaning liquid flowing through the cleaning-liquid circulation path by the deaeration device, and the bubbled dissolved air flows back to the cleaning tank together with the cleaning liquid so that the bubbled dissolved air is ejected from the liquid surface of the cleaning tank to the outside of the tank. Moreover, a propeller-type pump is used as the circulating pump, and the dissolved air concentration of the cleaning liquid is controlled within a range of 2.5 to 3.5 mg/l.

Abstract: The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.

Abstract: A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.

Abstract: A signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. A local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits and determines which of the second local bus, first local bus, and system bus will be connected to the local memory bus.