Patents by Inventor Masaru Kadoshima
Masaru Kadoshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145233Abstract: There is provided a technique that includes: (a) forming a non-flowable film on a surface of a substrate on which a recess is provided and an oxygen-containing film is exposed by supplying a first material to the substrate at a first temperature; and (b) forming a flowable film on the non-flowable film by supplying a second material to the substrate at a second temperature lower than the first temperature.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Applicant: Kokusai Electric CorporationInventors: Daigo YAMAGUCHI, Masaru KADOSHIMA
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Publication number: 20230411148Abstract: There is provided a technique that includes (a) forming an oligomer-containing layer on a surface of a substrate and in a concave portion of the substrate by allowing an oligomer to be generated, grow, and flow on the surface of the substrate and in the concave portion of the substrate by performing a cycle a predetermined number of times at a first temperature, the cycle including: supplying a precursor gas to the substrate; supplying a first nitrogen- and hydrogen-containing gas to the substrate; supplying a second nitrogen- and hydrogen-containing gas to the substrate; and supplying a first modifying gas to the substrate; and (b) forming a film by performing a thermal treatment to the substrate at a second temperature equal to or higher than the first temperature to modify the oligomer-containing layer so as to be filled in the concave portion.Type: ApplicationFiled: August 24, 2023Publication date: December 21, 2023Applicant: Kokusai Electric CorporationInventors: Atsushi SANO, Katsuyoshi HARADA, Daigo YAMAGUCHI, Masaru KADOSHIMA
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Publication number: 20230335398Abstract: According to one aspect of the technique of the present disclosure, there is provided a substrate processing method including: forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes: (a) supplying a source gas to the substrate; (b) supplying a plasma-excited gas containing nitrogen and hydrogen to the substrate by exciting a gas containing nitrogen and hydrogen into a plasma state; and (c) supplying a plasma-excited inert gas to the substrate by exciting an inert gas into a plasma state, wherein a pressure of a space where the substrate is present is set to be lower in (c) than in (b).Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Yuki TAIRA, Tsuyoshi TAKEDA, Masaru KADOSHIMA
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Publication number: 20230317420Abstract: There is provided a technique that includes: a) supplying a first gas to the substrate on which a film is formed and forming a modified layer on a surface of the film; b) after a), supplying a second gas to the modified layer and removing the modified layer; c) after b), supplying an inert gas having a first temperature higher than a processing temperature of b) to the film; and d) removing a portion of the film by performing a), b), and c) sequentially a predetermined number of times.Type: ApplicationFiled: September 30, 2022Publication date: October 5, 2023Applicant: Kokusai Electric CorporationInventors: Masaru KADOSHIMA, Atsushi SANO
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Patent number: 11094833Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.Type: GrantFiled: June 25, 2019Date of Patent: August 17, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masao Inoue, Masaru Kadoshima, Yoshiyuki Kawashima, Ichiro Yamakawa
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Patent number: 11081596Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.Type: GrantFiled: February 26, 2018Date of Patent: August 3, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20200027996Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.Type: ApplicationFiled: June 25, 2019Publication date: January 23, 2020Inventors: Masao INOUE, Masaru KADOSHIMA, Yoshiyuki KAWASHIMA, Ichiro YAMAKAWA
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Patent number: 10475883Abstract: In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.Type: GrantFiled: December 10, 2017Date of Patent: November 12, 2019Assignee: Renesas Electronics CorporationInventors: Masaru Kadoshima, Masahiko Fujisawa
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Publication number: 20180308964Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20180308991Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.Type: ApplicationFiled: February 26, 2018Publication date: October 25, 2018Applicant: Renesas Electronics CorporationInventors: Masaru KADOSHIMA, Masao INOUE
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Patent number: 10062773Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.Type: GrantFiled: May 14, 2015Date of Patent: August 28, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20180182850Abstract: In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.Type: ApplicationFiled: December 10, 2017Publication date: June 28, 2018Inventors: Masaru KADOSHIMA, Masahiko FUJISAWA
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Patent number: 9685565Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.Type: GrantFiled: August 27, 2014Date of Patent: June 20, 2017Assignee: Renesas Electronics CorporationInventors: Masaharu Mizutani, Masao Inoue, Hiroshi Umeda, Masaru Kadoshima
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Publication number: 20150340479Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.Type: ApplicationFiled: May 14, 2015Publication date: November 26, 2015Inventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20150060991Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.Type: ApplicationFiled: August 27, 2014Publication date: March 5, 2015Inventors: Masaharu Mizutani, Masao Inoue, Hiroshi Umeda, Masaru Kadoshima
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Patent number: 8536017Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.Type: GrantFiled: January 31, 2012Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Masaru Kadoshima, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
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Patent number: 8293632Abstract: To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film.Type: GrantFiled: April 6, 2010Date of Patent: October 23, 2012Assignee: Renesas Electronics CorporationInventors: Masaru Kadoshima, Shinsuke Sakashita, Takaaki Kawahara, Jiro Yugami
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Publication number: 20120252180Abstract: There is a problem with a CMIS semiconductor integrated circuit using a High-k Gate insulation film that, in a device region having a short channel length and a narrow channel width, with an increase of the film thickness of an Interfacial Layer IL between the High-k Gate insulation film and a silicon-based substrate by activation annealing of source/drain regions, the absolute value of the threshold voltage increases. One of the inventions of the present application is a manufacturing method of a semiconductor integrated circuit device having a MISFET. The method includes the steps of covering the semiconductor substrate surface with an oxygen absorption film after forming a gate stack of the MISFET and a peripheral structure of the MISFET, performing annealing in that state to activate impurities in the source/drain, and subsequently removing the oxygen absorption film.Type: ApplicationFiled: February 14, 2012Publication date: October 4, 2012Inventors: Takahiro TOMIMATSU, Masaru KADOSHIMA
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Publication number: 20120208346Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.Type: ApplicationFiled: January 31, 2012Publication date: August 16, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masaru KADOSHIMA, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
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Publication number: 20120056268Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.Type: ApplicationFiled: July 26, 2011Publication date: March 8, 2012Inventors: Masaharu MIZUTANI, Masaru KADOSHIMA, Takaaki KAWAHARA, Masao INOUE, Hiroshi UMEDA