Patents by Inventor Masaru Morita

Masaru Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230106784
    Abstract: In a double-side polishing apparatus includes at least one work thickness measuring instrument in real time during double-side polishing of the work; an inner circumferential surface defined by the through hole in said one of the upper plate and the lower plate is provided with a metal cylindrical member; and either of: a lower window provided in a lower part of the cylindrical member provided in the upper plate and an upper window provided in an upper part of the cylindrical member provided to cover the upper side of the through hole provided in the upper plate, or an upper window provided in an upper part of the cylindrical member provided in the lower plate and a lower window provided to cover the lower side of the through hole provided in the lower plate.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 6, 2023
    Applicant: SUMCO CORPORATION
    Inventors: Yuji MIYAZAKI, Masaru MORITA
  • Publication number: 20220189895
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a first electrode layer, and a first barrier layer provided on the first electrode layer and bonded to a metal layer, and a circuit substrate configured to include a second electrode layer, and a second barrier layer provided on the second electrode layer and bonded to the metal layer, wherein the semiconductor substrate including a semiconductor element, and the circuit substrate are bonded via the metal layer containing Sn, a linear expansion coefficient of the first barrier layer is larger than that of the circuit substrate, and a linear expansion coefficient of the second barrier layer is smaller than that of the circuit substrate.
    Type: Application
    Filed: August 13, 2021
    Publication date: June 16, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Masaru Morita
  • Patent number: 11276610
    Abstract: A wiring board includes a wiring layer; a diffusion suppressing layer that covers the wiring layer and suppresses diffusion of a metal component of the wiring layer; a base metal layer that covers the diffusion suppressing layer; and a passivation layer that covers the base metal layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Masaru Morita
  • Publication number: 20200343133
    Abstract: A wiring board includes a wiring layer; a diffusion suppressing layer that. covers the wiring layer and suppresses diffusion of a metal component of the wiring layer; a base metal layer that covers the diffusion suppressing layer; and a passivation layer that covers the base metal layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: October 29, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Masaru Morita
  • Publication number: 20200168563
    Abstract: An electronic device includes a substrate and a wiring. The wiring is provided above the substrate and includes a Ni—B layer and a copper layer provided on the Ni—B layer. The Ni—B layer contains 3.2% by weight to 5% by weight of boron.
    Type: Application
    Filed: October 2, 2019
    Publication date: May 28, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Masaru Morita, Yoshihiro Nakata
  • Publication number: 20190312122
    Abstract: An electronic component includes: a conductor portion containing a first element; a compound layer disposed around the conductor portion and containing a second element and a third element which are different from the first element; and an isolation layer, disposed between the conductor portion and the compound layer and containing a fourth element which is different from the first element, the second element, and the third element, to isolate the first element in the conductor portion from the second element and the third element outside the conductor portion.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 10, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaru Morita, Yoshihiro Nakata
  • Patent number: 9754904
    Abstract: An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: September 5, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Masaru Morita, Nobuhiro Imaizumi
  • Patent number: 9585246
    Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro Yoneda
  • Publication number: 20170047302
    Abstract: An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.
    Type: Application
    Filed: July 18, 2016
    Publication date: February 16, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Masaru Morita, Nobuhiro Imaizumi
  • Patent number: 9565755
    Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro Yoneda
  • Publication number: 20160192498
    Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro YONEDA
  • Publication number: 20160192479
    Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro YONEDA
  • Patent number: 9318425
    Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro Yoneda
  • Patent number: 8964402
    Abstract: An electronic device includes a wiring board including a first electrode and a second electrode, a semiconductor device mounted on the wiring board and including a first terminal and a second terminal, an interposer provided between the wiring board and the semiconductor device, the interposer including a conductive pad and a sheet supporting the conductive pad, the conductive pad having a first surface on a side of the wiring board and a second surface on a side of the semiconductor device, a first solder connecting the first electrode positioned outside of an area in which the interposer is disposed with the first terminal positioned outside of the area, a second solder connecting the second electrode positioned inside of the area with the first surface of the conductive pad, and a third solder connecting the second terminal positioned inside of the area with the second surface of the conductive pad.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro Yoneda
  • Patent number: 8598050
    Abstract: Disclosed are a laser annealing method and apparatus capable of forming a crystalline semiconductor thin film on the entire surface of a substrate without sacrificing the uniformity of crystallinity in a seam portion in a long-axis direction of laser light, the crystalline semiconductor thin film having good properties and high uniformity to an extent that the seam portion is not visually recognizable. During the irradiation of a linear beam, portions corresponding to the edges of the linear beam are shielded by a mask 10 which is disposed on the optical path of a laser light 2, and the mask 10 is operated so that the amount of shielding is periodically increased and decreased.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: December 3, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 8575515
    Abstract: A laser annealing apparatus is provided that is capable of reducing irradiation unevenness of laser light caused by a refraction phenomenon of the laser light due to fluctuation in the temperature of inert gas. The laser annealing apparatus includes a gas supply unit for supplying inert gas G to at least a laser irradiation area of a workpiece, and a gas temperature controller for regulating the temperature of the inert gas G. The gas temperature controller controls the temperature of the inert gas G supplied to the laser irradiation area so as to decrease a temperature difference between the temperature of the inert gas G and the atmospheric temperature of a space (a room R) that is disposed outside the supply area of the inert gas so the temperature controlled inert gas surrounds the optical path of the laser light.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: November 5, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Jun Izawa, Miyuki Masaki, Masaru Morita
  • Patent number: 8508031
    Abstract: An electronic device includes a wiring board; a semiconductor device arranged at an upper side of the wiring board with an electrically conductive member being arranged therebetween; a covering member arranged at an upper side of the semiconductor device; and a supporting member arranged at a lower side of the wiring board, the supporting member having a convex portion facing the wiring board, the supporting member being connected to the covering member and supporting the wiring board at the convex portion.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Limited
    Inventors: Nobuyuki Hayashi, Yasuhiro Yoneda, Teru Nakanishi, Masaru Morita
  • Patent number: 8472195
    Abstract: An electronic device includes an electronic component mounted on a substrate; a cooling system for cooling the electronic component; and a fastening structure for fastening the cooling system to the substrate. The fastening structure includes a first magnet provided to one of the substrate and the cooling system, a second magnetic material fixed to the other of the substrate and the cooling system and magnetically coupled with the first magnet, and a magnetic shield that covers a part or all of the first magnet except for a coupling face to be coupled with the second magnetic material.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Limited
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Katsusada Motoyoshi, Yasuhiro Yoneda
  • Patent number: 8446924
    Abstract: In the case of a lens array type homogenizer optical system, the incident angle and intensity of a laser beam 1 entering a large-sized lens (long-axis condenser lens 22) of a long-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while long-axis lens arrays 20a and 20b are reciprocated in a direction corresponding to a long axial direction of a linear beam (X-direction). Therefore, vertical stripes are significantly reduced. Further, the incident angle and intensity of a laser beam 1 entering a large-sized lens (projection lens 30) of a short-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while short-axis lens arrays 26a and 26b are reciprocated in a direction corresponding to a short axial direction of a linear beam (Y-direction). Therefore, horizontal stripes are significantly reduced.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 21, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 8276977
    Abstract: It is an object of the present invention to prevent a vehicle door from protruding into a vehicle cabin when a collision load is applied to the door from a lateral side thereof, and to reduce costs that are required for measures to prevent the door from protruding into the vehicle cabin.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 2, 2012
    Assignee: Toyota Shatai Kabushiki Kaisha
    Inventors: Yukio Tanaka, Masayuki Taguchi, Yasunari Sakai, Masaru Morita, Natsuki Kotera, Akikazu Hashizume