Abstract: In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×1012 cm?2 or less.

Abstract: A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

Abstract: A semiconductor device includes an IGBT region in which an IGBT element is formed and an FWD region in which an FWD element is formed. The IGBT region includes a first region and a second region different from the first region. The FWD region and the first region of the IGBT region have a carrier extraction portion that facilitates extraction of carriers injected from a second electrode compared to the second region when a forward bias for causing the FWD element to operate as a diode is applied between a first electrode and the second electrode.

Abstract: A semiconductor device has a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, a collector layer, a field stop layer, a first electrode and a second electrode. The base layer is disposed on the drift layer. The emitter region is disposed on a surface layer portion of the base layer. The gate insulation film is disposed between the drift layer and the emitter layer. The gate electrode is disposed on the gate insulation film. The collector layer is disposed at a portion of the drift layer opposite to the base layer. The field stop layer is disposed between the collector layer and the drift layer. The field stop layer has a higher carrier concentration than the drift layer. The first electrode is electrically connected to the base layer and the emitter region. The second electrode is electrically connected to the collector layer.

Abstract: A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

Abstract: A semiconductor apparatus includes a semiconductor substrate provided with a plurality of diode ranges and a plurality of IGBT ranges. The IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate. Each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with a lower electrode. The cathode regions and the current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range. Each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode. The collector region in each IGBT range is in contact with each cathode region in the adjacent diode range.

Abstract: A semiconductor device may include a semiconductor substrate, a plurality of trenches, an insulating film, a control electrode, an upper electrode, and a lower electrode. A diode region of the semiconductor substrate may include an n-type bypass region being in direct contact with each insulating film and connected to the upper electrode, a p-type anode contact region connected to the upper electrode, a p-type body region disposed below the bypass region and the anode contact region and being in direct contact with each insulating film below the bypass region, an n-type drift region being in direct contact with each insulating film below the body region, and an n-type cathode region disposed below the drift region and connected to the lower electrode. A position of a lower end of the anode contact region may be located below a position of a lower end of the bypass region.

Abstract: A semiconductor apparatus includes a semiconductor substrate provided with a plurality of diode ranges and a plurality of IGBT ranges. The IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate. Each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with a lower electrode. The cathode regions and the current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range. Each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode. The collector region in each IGBT range is in contact with each cathode region in the adjacent diode range.

Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode electrode provided above the semiconductor substrate; a resistance layer provided above the semiconductor substrate and having a resistivity higher than the sense anode electrode; a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode comprises a first anode region of a p-type connected to the sense anode electrode via the resistance layer and a first cathode region of an n-type connected to the lower main electrode.

Abstract: A diode includes a first-conductivity-type barrier region disposed between a drift region and a second impurity region and having an impurity concentration higher than that of the drift region and a second-conductivity-type field extension prevention region disposed between the barrier region and the drift region. The diode also includes a trench gate disposed to extend from a second main surface of a semiconductor substrate through the second impurity region and the barrier region and reach the field extension prevention region. The trench gate has a gate electrode for applying a gate voltage. A gate electrode is applied with a parasitic gate voltage, as the gate voltage. The parasitic gate voltage has an absolute value of a potential difference with a second electrode being equal to or greater than a threshold voltage of a parasitic transistor formed of the second impurity region, the barrier region, and the field extension prevention region.

Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.

Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.

Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode electrode provided above the semiconductor substrate; a resistance layer provided above the semiconductor substrate and having a resistivity higher than the sense anode electrode; a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode comprises a first anode region of a p-type connected to the sense anode electrode via the resistance layer and a first cathode region of an n-type connected to the lower main electrode.

Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.

Abstract: A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

Abstract: A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.

Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.

Abstract: A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

Abstract: An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.

Abstract: An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.