Abstract: In duplicated equipment including main equipment, duplicated subordinate equipment, and a communication line for transferring data between the main equipment and the duplicated subordinate equipment and for sending a changeover signal which can put one and the other of a pair of subordinate devices making up the duplicated subordinate equipment in an active state and a standby state, respectively, from the main equipment to the duplicated subordinate equipment, each of the subordinate devices includes means for putting the other subordinate device in the standby state, to prevent both of the subordinate devices from being put in the active state when a failure occurs on a transmission path between the communication line and one of the subordinate devices.

Abstract: In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction. After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signals.

Abstract: In a system comprising a memory, an input/output control device, a direct memory access controller and a data bus, the transfer of data between the memory and the input/output control device via the data bus by means of said direct memory access controller during the period of direct memory access mode is effected by controlling the data transfer direction on a data bus so that a control signal for determining the direction of transferring the data by said data bus is recognized in an inverted manner at the memory or the input/output control device only during the period of a data transfer cycle in the direct memory access mode.