Abstract: A flash memory capable of achieving high integration and low power consumption is formed by an AND-type memory cell array, an address buffer, a row selecting/driving circuit, a column selecting circuit, an input and output circuit, and a read/write control part. A memory cell includes, for example, a charge storage layer of an ONO structure. The read/write control part performs programming and erasing by Fowler-Nordheim (FN) tunneling between the charge storage layer and a channel of a selected memory cell.

Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.

Abstract: Disclosed is a flash memory, which includes: a memory cell array including two planes; a controller configured to control the read action and program action of the two planes; and two latches configured to hold data read from one plane or data that should be programmed to one plane; and two latches configured to hold data read from another plane or data that should be programmed to another plane. The controller is configured to perform read operation of the other plane according to a simultaneous command input from the outside while performing programming operation of one plane.

Abstract: The disclosure provides a semiconductor device and a programming method capable of programming with reduced power consumption. The programming method of the NAND flash memory of the disclosure prepares high-speed programming blocks and copy back block for final data storage, responding to an external input programming command while in an power-saving mode, program 1/2 pages of data in even-numbered pages and odd-numbered pages of the high-speed programming blocks respectively, then the data is read out from the high-speed programming blocks, and the read data is normally programmed into the copy back block.

Abstract: A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.

Abstract: The disclosure provides a semiconductor device and an erasing method that may alleviate the deterioration of a memory cell caused by ISPE. The NAND flash memory in the disclosure includes a memory cell array and an erasing component that erases selected blocks of the memory cell array. The erasing component performs a first erasing verification (EV1) and a second erasing verification (EV2) on the selected block. When the first erasing verification (EV1) passes, and the second erasing verification (EV2) fails, an erase pulse with the same erase voltage as the last time is applied, and when the first erasing verification (EV1) fails, an erase pulse with a step voltage higher than the last time is applied.

Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.

Abstract: A semiconductor memory device capable of automatically restoring writing interrupted due to a momentary stop or a fluctuation of a power supply voltage is provided. A non-volatile memory of the disclosure includes a memory cell array formed with a NOR array and a variable resistance array. When the power supply voltage drops to a power-off level during writing into the NOR array, a reading/writing control unit writes unwritten data into the variable resistance array. Subsequently, when a power-on of the power supply voltage is detected, the reading/writing control unit reads the unwritten data from the variable resistance array and writes the unwritten data into the NOR array, so that interrupted writing is restored.

Abstract: A semiconductor memory device has a NOR-type memory cell array, a crossbar array, an entry gate, and a column selecting/signal processing unit. The crossbar array has a plurality of rows and columns, variable resistor elements formed in intersections of rows and columns respectively. The entry gate arranged between the memory cell array and the crossbar array, connects a selected bit line of the memory cell array to the crossbar array based on a selection signal. The column selecting/signal processing unit has a column writing unit, a column reading unit, and a NOR writing unit. The column writing unit writes data read from the memory cell array to a selected column of the crossbar array. The column reading unit reads data of the selected column of the crossbar array. The NOR writing unit at least writes data read by the column writing unit to the memory cell array.

Abstract: An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.

Abstract: A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.

Abstract: A semiconductor storage device capable of achieving low power and high integration is provided. A non-volatile semiconductor memory of the disclosure includes a memory cell array. The memory cell array has a NOR array with a NOR flash memory structure and a variable resistance array with a variable resistance memory structure formed on a substrate. An entry gate is formed between the NOR array and the variable resistance array. When the NOR array is accessed, the entry gate separates the variable resistance array from the NOR array.

Abstract: The disclosure provides a semiconductor device and an erasing method that may control a number of times an erase pulse is applied. The erasing method of a flash memory of the disclosure includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.

Abstract: Provided is a resistive random-access memory device, including: multiple pillars, extending in a vertical direction with respect to a main surface of a substrate; multiple bit lines, extending in a horizontal direction with respect to the main surface of the substrate; and a memory cell, formed at an intersection of the pillars and the bit lines. The memory cell includes a gate insulating film formed on an outer periphery of the pillars, a semiconductor film formed on an outer periphery of the gate insulating film and providing a channel region, and a variable resistance element formed on a part of an outer periphery of the semiconductor film. An electrode region of an outer periphery of the variable resistance element is connected to one of a pair of adjacent bit lines, and the semiconductor film is connected to the other of the pair of adjacent bit lines.

Abstract: Provide a resistive random-access memory device having an optimized 3D construction. A resistive random-access memory includes a plurality of pillars, a plurality of bit lines, and a memory cell. The pillars extend vertically along the main surface of the substrate. The bit lines extend in a horizontal direction. The memory cell is formed at the intersection of the pillars and the bit lines. The memory cell includes a gate insulating film, a semiconductor film, and a resistive element. The gate insulating film is formed on the circumference of the pillar. The semiconductor film is formed on the circumference of gate insulating film and provides a channel area. The resistive element is formed on the circumference of the semiconductor film. A first electrode area on the circumference of the resistive element and a second electrode area facing the first electrode area are electrically connected to a pair of adjacent bit lines.

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.

Abstract: An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.

Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.

Abstract: A resistance variable type synapse array apparatus that can perform STDP writing using a positive potential is provided. The synapse array apparatus includes a writing unit writing to a selected resistance variable type memory element in a crossbar array. The writing unit includes a driver generating a positive pulse signal corresponding to a positive part of a spike signal generated by a presynaptic neuron, a driver generating a positive pulse signal corresponding to a negative part of a spike signal generated by a postsynaptic neuron, a driver generating a positive pulse signal corresponding to a positive part of the spike signal generated by the postsynaptic neuron, and a driver generating a positive pulse signal corresponding to a negative part of the spike signal generated by the presynaptic neuron.