Abstract: A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators. The clock signal generation device includes a voltage controlled oscillator for generating a clock signal corresponding to each of a plurality of oscillation characteristics. The clock signal generation device applies a test voltage to a voltage controlled oscillator with a voltage control device and sequentially identifies a plurality of oscillation characteristics set for the voltage controlled oscillator. The clock signal generation device selects one of the identified oscillation characteristics that has a frequency range with a generally middle part in which the frequency of a wobble signal is located and has a smaller gain.

Abstract: A PLL circuit for generating a clock signal using a reference signal, the frequency of which is relatively low. The PLL circuit includes a first loop circuit for generating a first clock signal which is synchronized with a first reference signal. A second loop circuit generates a second clock signal which is synchronized with a second reference signal. The frequency of the second reference signal is sufficiently lower than the frequency of the first reference signal. The first reference signal is compared with the first clock signal to generate a first control voltage. The second reference signal is compared with the second clock signal to generate a second control voltage. The second loop circuit generates the second clock signal in accordance with the first control voltage and the second control voltage.

Abstract: A voltage-controlled oscillator (VCO) enabling proper gain adjustment with a simple configuration. The VCO includes a first current source for generating a first control current in accordance with the first control voltage and a second current source for generating a second control current in accordance with the second control voltage. A control voltage generation circuit synthesizes the first and second control currents to generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator generates an oscillation signal with a frequency corresponding to the oscillation control voltage. The first current source varies a changing amount of the first control current relative to a change in the first control voltage. The second current source varies a changing amount of the second control current relative to a change in the second control voltage.

Abstract: A PLL circuit for generating a clock signal synchronized with a first reference signal generated by superimposing a wobble signal on a land pre-pit signal or a second reference signal generated from a wobble signal. The PLL circuit enables reduction in circuit scale. When a DVD-R/RW is used as an optical disc, a first loop synchronizes the frequency of a wobble signal with the frequency of a divisional clock signal, which is generated from a recording clock signal of a voltage-controlled oscillator. Further, a second loop synchronizes the phase of the divisional clock signal with the phase of the LPP signal. When a DVD+R/RW is used as an optical disc, the first loop synchronizes the frequency of the divisional clock signal with the frequency of the wobble signal. Further, the second loop applies constant voltage to a control voltage input terminal of the voltage-controlled oscillator.

Abstract: A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators. The clock signal generation device includes a voltage controlled oscillator for generating a clock signal corresponding to each of a plurality of oscillation characteristics. The clock signal generation device applies a test voltage to a voltage controlled oscillator with a voltage control device and sequentially identifies a plurality of oscillation characteristics set for the voltage controlled oscillator. The clock signal generation device selects one of the identified oscillation characteristics that has a frequency range with a generally middle part in which the frequency of a wobble signal is located and has a smaller gain.

Abstract: A PLL circuit that optimally generates a clock signal with two reference signals having different frequencies. The PLL circuit includes a VCO for generating the clock signal in accordance with a control voltage. A first loop controls the frequency of the clock signal in accordance with a first reference signal. A second loop controls the phase of the clock signal in accordance with a second reference signal, whose cycle is longer than that of the first reference signal. The second loop supplies the VCO with the control voltage at a constant value until the difference between the frequencies of the first reference and clock signals converges to within a predetermined range. Then, the second loop supplies the VCO with a control voltage at a level corresponding to the difference between the phases of the second reference and clock signals.

Abstract: A PLL circuit for generating a clock signal synchronized with a first reference signal generated by superimposing a wobble signal on a land pre-pit signal or a second reference signal generated from a wobble signal. The PLL circuit enables reduction in circuit scale. When a DVD-R/RW is used as an optical disc, a first loop synchronizes the frequency of a wobble signal with the frequency of a divisional clock signal, which is generated from a recording clock signal of a voltage-controlled oscillator. Further, a second loop synchronizes the phase of the divisional clock signal with the phase of the LPP signal. When a DVD+R/RW is used as an optical disc, the first loop synchronizes the frequency of the divisional clock signal with the frequency of the wobble signal. Further, the second loop applies constant voltage to a control voltage input terminal of the voltage-controlled oscillator.

Abstract: A voltage-controlled oscillator (VCO) enabling proper gain adjustment with a simple configuration. The VCO includes a first current source for generating a first control current in accordance with the first control voltage and a second current source for generating a second control current in accordance with the second control voltage. A control voltage generation circuit synthesizes the first and second control currents to generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator generates an oscillation signal with a frequency corresponding to the oscillation control voltage. The first current source varies a changing amount of the first control current relative to a change in the first control voltage. The second current source varies a changing amount of the second control current relative to a change in the second control voltage.

Abstract: A PLL circuit that optimally generates a clock signal with two reference signals having different frequencies. The PLL circuit includes a VCO for generating the clock signal in accordance with a control voltage. A first loop controls the frequency of the clock signal in accordance with a first reference signal. A second loop controls the phase of the clock signal in accordance with a second reference signal, whose cycle is longer than that of the first reference signal. The second loop supplies the VCO with the control voltage at a constant value until the difference between the frequencies of the first reference and clock signals converges to within a predetermined range. Then, the second loop supplies the VCO with a control voltage at a level corresponding to the difference between the phases of the second reference and clock signals.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.

Abstract: A PLL circuit for generating a clock signal using a reference signal, the frequency of which is relatively low. The PLL circuit includes a first loop circuit for generating a first clock signal which is synchronized with a first reference signal. A second loop circuit generates a second clock signal which is synchronized with a second reference signal. The frequency of the second reference signal is sufficiently lower than the frequency of the first reference signal. The first reference signal is compared with the first clock signal to generate a first control voltage. The second reference signal is compared with the second clock signal to generate a second control voltage. The second loop circuit generates the second clock signal in accordance with the first control voltage and the second control voltage.

Abstract: A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation lock signal is synchronous with the reference clock. If the phase lock detector detects a phase difference between the oscillation clock signal and the reference clock, a charge pump circuit is used to alter the oscillation clock signal so that the oscillation signal is placed back in sync with the reference clock. The charge pump selects one of a ground potential and a power supply potential in response to a comparison result of the oscillation clock signal and the reference clock. The charge pump pulls a constant current to ground from an output terminal of the charge pump ,circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.

Abstract: An image data processing apparatus is described that prevents the period of a horizontal timing signal from being shifted. The apparatus includes a separator, a phase-locked loop, a detector, a compensator and a timing signal generator. The detector delays a reference clock signal in a shorter period than the period of the reference clock signal, in a step-like manner, to produce a plurality of delayed timing signals having step-like phase differences. The detector further contrasts the plurality of delayed timing signals with a horizontal sync signal and the reference clock signal to measure the phase difference and the period of the horizontal sync signal. The compensator sets a ratio for combining consecutive luminance data in accordance with the phase difference and the period of the reference clock signal and combines consecutive luminance data in accordance with the ratio to generate compensated luminance data.