Abstract: The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having an active area and a source electrode formed on the semiconductor substrate. The source electrode is covered by a hard passivation layer and an opening is formed in the hard passivation layer. An under bump metal (UBM) layer used as a barrier film is formed broader than the opening to reduce a spreading resistance during the operation of the semiconductor device and a warp amount of the semiconductor substrate caused by variation of temperature.

Abstract: The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.

Abstract: According to an embodiment of the invention, an apparatus includes a microprocessor-based pulse-width modulation controller configured to generate a pulse-width modulation signal, and a synchronous converter including a first transistor, a second transistor, a first driver, and a second driver. The apparatus further includes a drive voltage generator configured to generate a drive voltage for the synchronous converter. The drive voltage generator is further configured to generate the drive voltage based on a measured output current and a measured input voltage.

Abstract: According to an embodiment of the invention, an apparatus includes a microprocessor-based pulse-width modulation controller configured to generate a pulse-width modulation signal, and a synchronous converter including a first transistor, a second transistor, a first driver, and a second driver. The apparatus further includes a drive voltage generator configured to generate a drive voltage for the synchronous converter. The drive voltage generator is further configured to generate the drive voltage based on a measured output current and a measured input voltage.

Abstract: Two vertical-type power MISFETs are formed over a semiconductor chip, a common drain electrode formed over a back surface of the semiconductor chip is electrically connected with a drain terminal via a conductive bonding material, source electrodes and gate electrodes formed over a surface of the semiconductor chip are respectively electrically connected with source terminals and gate terminals via bump electrodes, and these components are sealed by a resin sealing portion. The exposed portions of the gate terminals are arranged inside the resin sealing portion, and the exposed portions of the source terminals are arranged outside the resin sealing portion. The source terminals extend over the surface of the semiconductor chip and are connected with the source electrodes which are uniformly arranged over regions of the surface of the semiconductor chip except for gate electrode forming regions and the vicinities of these regions via the bump electrodes.

Abstract: Two vertical-type power MISFETs are formed over a semiconductor chip, a common drain electrode formed over a back surface of the semiconductor chip is electrically connected with a drain terminal via a conductive bonding material, source electrodes and gate electrodes formed over a surface of the semiconductor chip are respectively electrically connected with source terminals and gate terminals via bump electrodes, and these components are sealed by a resin sealing portion. The exposed portions of the gate terminals are arranged inside the resin sealing portion, and the exposed portions of the source terminals are arranged outside the resin sealing portion. The source terminals extend over the surface of the semiconductor chip and are connected with the source electrodes which are uniformly arranged over regions of the surface of the semiconductor chip except for gate electrode forming regions and the vicinities of these regions via the bump electrodes.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.