Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: An output feedback control circuit includes, as a means for generating an error signal ERR between a feedback voltage FB commensurate with an output voltage and a reference voltage REF (means for substituting for a single error amplifier 140), a first signal processor (for example, an amplifier 140a) that forms a first path, and a second signal processor (for example, an amplifier 140b) that forms a second path. The amplifier 140a is more accurate than the amplifier 140b, and the amplifier 140b is faster than the amplifier 140a. To the output terminal of the amplifier 140a, preferably, a capacitor Cc other than a parasitic element is connected. To the output terminal of the amplifier 140b, preferably, no capacitor other than a parasitic element is connected, and a resistor Rc is connected. Preferably, the amplifier 140a has a transconductance gm1, and the amplifier 140b has a transconductance gm2 (?gm1).

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

Abstract: A switching power supply includes: a switching output circuit configured to generate an output voltage from an input voltage by charging a capacitor by turning on and off an output transistor; a control circuit configured to halt the driving of the switching output circuit when charging electric charge to the capacitor per switching event is limited to a lower limit value and the output voltage, or a feedback voltage commensurate therewith, is raised from a predetermined reference voltage; and a lower limit value setting circuit configured to variably control the lower limit value during the driven period of the switching output circuit. For example, the lower limit value setting circuit can increase the lower limit value with increase in the number of times of switching.

Abstract: A switching power supply includes: a switching output circuit configured to generate an output voltage from an input voltage by charging a capacitor by turning on and off an output transistor; a control circuit configured to halt the driving of the switching output circuit when charging electric charge to the capacitor per switching event is limited to a lower limit value and the output voltage, or a feedback voltage commensurate therewith, is raised from a predetermined reference voltage; and a lower limit value setting circuit configured to variably control the lower limit value during the driven period of the switching output circuit. For example, the lower limit value setting circuit can increase the lower limit value with increase in the number of times of switching.

Abstract: This semiconductor device has a plurality of external terminals arranged in an array on a bottom surface of a package. The plurality of external terminals include a first external terminal group for receiving an input of a current from outside the device, and a second external terminal group for outputting a current to the outside of the device. The first external terminal group and the second external terminal group are laid out such that respective arrangement patterns thereof are interlocked with each other. The arrangement patterns may be comb-tooth shaped, cross-shaped, S-shaped, T-shaped, L-shaped, or may have a shape comprising a combination thereof. The plurality of external terminals may be pins, solder balls, or electrode pads.

Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.

Abstract: This semiconductor device has a plurality of external terminals arranged in an array on a bottom surface of a package. The plurality of external terminals include a first external terminal group for receiving an input of a current from outside the device, and a second external terminal group for outputting a current to the outside of the device. The first external terminal group and the second external terminal group are laid out such that respective arrangement patterns thereof are interlocked with each other. The arrangement patterns may be comb-tooth shaped, cross-shaped, S-shaped, T-shaped, L-shaped, or may have a shape comprising a combination thereof. The plurality of external terminals may be pins, solder balls, or electrode pads.

Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.

Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.

Abstract: A high-side variable current source and a high-side transistor are provided in series between a supply power terminal of a control circuit and a gate of a switching transistor. A low-side variable current source and a low-side transistor are provided in series between the gate of the switching transistor and a ground terminal. A slew rate controller controls the current value of at least one of the high-side and low-side variable current sources according to the state of a setting terminal. A switching power supply device has a plurality of output transistors connected in parallel with one another and a controller that generates control signals turning on and off the output transistors at a predetermined frequency so as to generate a desired output voltage from an input voltage and supply the output voltage to a load. The controller determines which output transistor to drive according to the magnitude of the load.

Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.

Abstract: A multi-output power supply device (1) comprises a first power supply (10) for outputting a first output voltage (VDCO1); a second power supply (30) for outputting a second output voltage (VDCO3); and a reset circuit (40) for detecting an abnormality of the first output voltage (VDCO1) and for outputting a first reset signal (XRESET) to forcibly stop the output operation of the second power supply (30).

Abstract: The step-up DC/DC converter (30) of the present invention has a synchronous rectifier transistor (M1); an output transistor (M2); a first back-gate control transistor (M3) connected between an external terminal (T2) and a back gate of the synchronous rectifier transistor (M1); a discharge transistor (M6) connected between the external terminal (T2) and a ground terminal; and a control unit (X1) for controlling the on/off state of the components described above. The control unit (X1) switches off the first back-gate control transistor (M3) and switches on the discharge transistor (M6) when stopping the switching operation of the output transistor (M2) and the synchronous rectifier transistor (M1).

Abstract: A high-side variable current source and a high-side transistor are provided in series between a supply power terminal of a control circuit and a gate of a switching transistor. A low-side variable current source and a low-side transistor are provided in series between the gate of the switching transistor and a ground terminal. A slew rate controller controls the current value of at least one of the high-side and low-side variable current sources according to the state of a setting terminal. A switching power supply device has a plurality of output transistors connected in parallel with one another and a controller that generates control signals turning on and off the output transistors at a predetermined frequency so as to generate a desired output voltage from an input voltage and supply the output voltage to a load. The controller determines which output transistor to drive according to the magnitude of the load.